[llvm] r215749 - R600/SI: Move all fabs / fneg handling to patterns
Matt Arsenault
Matthew.Arsenault at amd.com
Fri Aug 15 11:42:22 PDT 2014
Author: arsenm
Date: Fri Aug 15 13:42:22 2014
New Revision: 215749
URL: http://llvm.org/viewvc/llvm-project?rev=215749&view=rev
Log:
R600/SI: Move all fabs / fneg handling to patterns
Modified:
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
llvm/trunk/lib/Target/R600/SIInstructions.td
llvm/trunk/test/CodeGen/R600/fabs.ll
llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll
llvm/trunk/test/CodeGen/R600/fneg-fabs.ll
llvm/trunk/test/CodeGen/R600/or.ll
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=215749&r1=215748&r2=215749&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Fri Aug 15 13:42:22 2014
@@ -644,95 +644,6 @@ MachineBasicBlock * SITargetLowering::Em
MI->eraseFromParent();
break;
}
- case AMDGPU::FABS_SI: {
- MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
- const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
- getTargetMachine().getSubtargetImpl()->getInstrInfo());
- DebugLoc DL = MI->getDebugLoc();
- unsigned DestReg = MI->getOperand(0).getReg();
- unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
- .addImm(0x7fffffff);
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
- .addReg(MI->getOperand(1).getReg())
- .addReg(Reg);
- MI->eraseFromParent();
- break;
- }
- case AMDGPU::FABS64_SI: {
- MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
- const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
- getTargetMachine().getSubtargetImpl()->getInstrInfo());
-
- DebugLoc DL = MI->getDebugLoc();
- unsigned SuperReg = MI->getOperand(0).getReg();
- unsigned SrcReg = MI->getOperand(1).getReg();
-
- unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
- // Copy the subregister to make sure it is the right register class.
- unsigned VReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
- BuildMI(*BB, I, DL, TII->get(AMDGPU::COPY), VReg)
- .addReg(SrcReg, 0, AMDGPU::sub1);
-
- // We only need to mask the upper half of the register pair.
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), TmpReg)
- .addImm(0x7fffffff)
- .addReg(VReg);
-
- BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
- .addReg(SrcReg, 0, AMDGPU::sub0)
- .addImm(AMDGPU::sub0)
- .addReg(TmpReg)
- .addImm(AMDGPU::sub1);
- MI->eraseFromParent();
- break;
- }
- case AMDGPU::FNEG_SI: {
- MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
- const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
- getTargetMachine().getSubtargetImpl()->getInstrInfo());
- DebugLoc DL = MI->getDebugLoc();
- unsigned DestReg = MI->getOperand(0).getReg();
- unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
- // FIXME: Should use SALU instructions
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
- .addImm(0x80000000);
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
- .addReg(MI->getOperand(1).getReg())
- .addReg(Reg);
- MI->eraseFromParent();
- break;
- }
- case AMDGPU::FNEG64_SI: {
- MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
- const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
- getTargetMachine().getSubtargetImpl()->getInstrInfo());
-
- DebugLoc DL = MI->getDebugLoc();
- unsigned SrcReg = MI->getOperand(1).getReg();
- unsigned DestReg = MI->getOperand(0).getReg();
-
- unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
- unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
- // FIXME: Should use SALU instructions
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), ImmReg)
- .addImm(0x80000000);
- BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), TmpReg)
- .addReg(SrcReg, 0, AMDGPU::sub1)
- .addReg(ImmReg);
-
- BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), DestReg)
- .addReg(SrcReg, 0, AMDGPU::sub0)
- .addImm(AMDGPU::sub0)
- .addReg(TmpReg)
- .addImm(AMDGPU::sub1);
- MI->eraseFromParent();
- break;
- }
case AMDGPU::FCLAMP_SI: {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
getTargetMachine().getSubtargetImpl()->getInstrInfo());
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=215749&r1=215748&r2=215749&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Fri Aug 15 13:42:22 2014
@@ -2322,48 +2322,51 @@ def : Pat <
/********** Floating point absolute/negative **********/
/********** ================================ **********/
-// Manipulate the sign bit directly, as e.g. using the source negation modifier
-// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
-// breaking the piglit *s-floatBitsToInt-neg* tests
+// Prevent expanding both fneg and fabs.
-// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
-// removing these patterns
+// FIXME: Should use S_OR_B32
def : Pat <
(fneg (fabs f32:$src)),
(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
>;
+// FIXME: Should use S_OR_B32
def : Pat <
(fneg (fabs f64:$src)),
(f64 (INSERT_SUBREG
(INSERT_SUBREG (f64 (IMPLICIT_DEF)),
(i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
- (V_OR_B32_e32 (S_MOV_B32 0x80000000),
- (EXTRACT_SUBREG f64:$src, sub1)), sub1)) // Set sign bit.
+ (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
+ (V_MOV_B32_e32 0x80000000)), sub1)) // Set sign bit.
>;
-class SIUnaryCustomInsertInst<string name, SDPatternOperator node,
- ValueType vt,
- RegisterClass dstrc,
- RegisterClass srcrc> :
- AMDGPUShaderInst<
- (outs dstrc:$dst),
- (ins srcrc:$src0),
- name#" $dst, $src0",
- [(set vt:$dst, (node vt:$src0))]> {
- let usesCustomInserter = 1;
-}
-
-def FABS_SI : SIUnaryCustomInsertInst<"FABS_SI", fabs,
- f32, VReg_32, VSrc_32>;
-def FNEG_SI : SIUnaryCustomInsertInst<"FNEG_SI", fneg,
- f32, VReg_32, VSrc_32>;
-
-def FABS64_SI : SIUnaryCustomInsertInst<"FABS64_SI", fabs,
- f64, VReg_64, VSrc_64>;
-def FNEG64_SI : SIUnaryCustomInsertInst<"FNEG64_SI", fneg,
- f64, VReg_64, VSrc_64>;
+def : Pat <
+ (fabs f32:$src),
+ (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
+>;
+
+def : Pat <
+ (fneg f32:$src),
+ (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
+>;
+
+def : Pat <
+ (fabs f64:$src),
+ (f64 (INSERT_SUBREG
+ (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
+ (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
+ (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
+ (V_MOV_B32_e32 0x7fffffff)), sub1)) // Set sign bit.
+>;
+def : Pat <
+ (fneg f64:$src),
+ (f64 (INSERT_SUBREG
+ (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
+ (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
+ (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
+ (V_MOV_B32_e32 0x80000000)), sub1))
+>;
/********** ================== **********/
/********** Immediate Patterns **********/
Modified: llvm/trunk/test/CodeGen/R600/fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fabs.ll?rev=215749&r1=215748&r2=215749&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fabs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fabs.ll Fri Aug 15 13:42:22 2014
@@ -72,7 +72,7 @@ define void @fabs_v4f32(<4 x float> addr
; SI-LABEL: @fabs_fn_fold
; SI: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; SI-NOT: V_AND_B32_e32
+; SI-NOT: AND
; SI: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
%fabs = call float @fabs(float %in0)
@@ -83,7 +83,7 @@ define void @fabs_fn_fold(float addrspac
; SI-LABEL: @fabs_fold
; SI: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; SI-NOT: V_AND_B32_e32
+; SI-NOT: AND
; SI: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
%fabs = call float @llvm.fabs.f32(float %in0)
Modified: llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll?rev=215749&r1=215748&r2=215749&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll Fri Aug 15 13:42:22 2014
@@ -4,7 +4,8 @@
; into 2 modifiers, although theoretically that should work.
; FUNC-LABEL: @fneg_fabs_fadd_f64
-; SI: V_AND_B32_e32 v[[FABS:[0-9]+]], 0x7fffffff, {{v[0-9]+}}
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x7fffffff
+; SI: V_AND_B32_e32 v[[FABS:[0-9]+]], {{s[0-9]+}}, [[IMMREG]]
; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}}
define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
%fabs = call double @llvm.fabs.f64(double %x)
@@ -44,7 +45,8 @@ define void @fneg_fabs_free_f64(double a
}
; FUNC-LABEL: @fneg_fabs_fn_free_f64
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
%bc = bitcast i64 %in to double
%fabs = call double @fabs(double %bc)
@@ -54,6 +56,12 @@ define void @fneg_fabs_fn_free_f64(doubl
}
; FUNC-LABEL: @fneg_fabs_f64
+; SI: S_LOAD_DWORDX2
+; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI-DAG: V_OR_B32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
+; SI-DAG: V_MOV_B32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
+; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
%fabs = call double @llvm.fabs.f64(double %in)
%fsub = fsub double -0.000000e+00, %fabs
@@ -62,8 +70,10 @@ define void @fneg_fabs_f64(double addrsp
}
; FUNC-LABEL: @fneg_fabs_v2f64
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI-NOT: 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
%fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
@@ -72,10 +82,12 @@ define void @fneg_fabs_v2f64(<2 x double
}
; FUNC-LABEL: @fneg_fabs_v4f64
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
-; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI-NOT: 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
%fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
Modified: llvm/trunk/test/CodeGen/R600/fneg-fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fneg-fabs.ll?rev=215749&r1=215748&r2=215749&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fneg-fabs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fneg-fabs.ll Fri Aug 15 13:42:22 2014
@@ -1,6 +1,28 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
+; FUNC-LABEL: @fneg_fabs_fadd_f32
+; SI-NOT: AND
+; SI: V_SUB_F32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}|
+define void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) {
+ %fabs = call float @llvm.fabs.f32(float %x)
+ %fsub = fsub float -0.000000e+00, %fabs
+ %fadd = fadd float %y, %fsub
+ store float %fadd, float addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: @fneg_fabs_fmul_f32
+; SI-NOT: AND
+; SI: V_MUL_F32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}|
+; SI-NOT: AND
+define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
+ %fabs = call float @llvm.fabs.f32(float %x)
+ %fsub = fsub float -0.000000e+00, %fabs
+ %fmul = fmul float %y, %fsub
+ store float %fmul, float addrspace(1)* %out, align 4
+ ret void
+}
; DAGCombiner will transform:
; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
@@ -11,7 +33,8 @@
; R600: |PV.{{[XYZW]}}|
; R600: -PV
-; SI: V_OR_B32
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
%bc = bitcast i32 %in to float
%fabs = call float @llvm.fabs.f32(float %bc)
@@ -25,7 +48,8 @@ define void @fneg_fabs_free_f32(float ad
; R600: |PV.{{[XYZW]}}|
; R600: -PV
-; SI: V_OR_B32
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
%bc = bitcast i32 %in to float
%fabs = call float @fabs(float %bc)
@@ -34,14 +58,37 @@ define void @fneg_fabs_fn_free_f32(float
ret void
}
+; FUNC-LABEL: @fneg_fabs_f32
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
+define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
+ %fabs = call float @llvm.fabs.f32(float %in)
+ %fsub = fsub float -0.000000e+00, %fabs
+ store float %fsub, float addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: @v_fneg_fabs_f32
+; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
+define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
+ %val = load float addrspace(1)* %in, align 4
+ %fabs = call float @llvm.fabs.f32(float %val)
+ %fsub = fsub float -0.000000e+00, %fabs
+ store float %fsub, float addrspace(1)* %out, align 4
+ ret void
+}
+
; FUNC-LABEL: @fneg_fabs_v2f32
; R600: |{{(PV|T[0-9])\.[XYZW]}}|
; R600: -PV
; R600: |{{(PV|T[0-9])\.[XYZW]}}|
; R600: -PV
-; SI: V_OR_B32
-; SI: V_OR_B32
+; FIXME: SGPR should be used directly for first src operand.
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI-NOT: 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
%fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
@@ -49,11 +96,14 @@ define void @fneg_fabs_v2f32(<2 x float>
ret void
}
+; FIXME: SGPR should be used directly for first src operand.
; FUNC-LABEL: @fneg_fabs_v4f32
-; SI: V_OR_B32
-; SI: V_OR_B32
-; SI: V_OR_B32
-; SI: V_OR_B32
+; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
+; SI-NOT: 0x80000000
+; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
+; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
%fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
Modified: llvm/trunk/test/CodeGen/R600/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/or.ll?rev=215749&r1=215748&r2=215749&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/or.ll (original)
+++ llvm/trunk/test/CodeGen/R600/or.ll Fri Aug 15 13:42:22 2014
@@ -56,6 +56,32 @@ define void @vector_or_i32(i32 addrspace
ret void
}
+; SI-LABEL: @scalar_or_literal_i32
+; SI: S_OR_B32 s0, s0, 0x1869f
+define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
+ %or = or i32 %a, 99999
+ store i32 %or, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; SI-LABEL: @vector_or_literal_i32
+; SI: V_OR_B32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
+define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
+ %loada = load i32 addrspace(1)* %a, align 4
+ %or = or i32 %loada, 65535
+ store i32 %or, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; SI-LABEL: @vector_or_inline_immediate_i32
+; SI: V_OR_B32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
+define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
+ %loada = load i32 addrspace(1)* %a, align 4
+ %or = or i32 %loada, 4
+ store i32 %or, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
; EG-LABEL: @scalar_or_i64
; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
More information about the llvm-commits
mailing list