[llvm] r215747 - R600/SI: Use source modifier for f64 fabs
Matt Arsenault
Matthew.Arsenault at amd.com
Fri Aug 15 11:42:15 PDT 2014
Author: arsenm
Date: Fri Aug 15 13:42:15 2014
New Revision: 215747
URL: http://llvm.org/viewvc/llvm-project?rev=215747&view=rev
Log:
R600/SI: Use source modifier for f64 fabs
Added:
llvm/trunk/test/CodeGen/R600/fabs.f64.ll
Modified:
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=215747&r1=215746&r2=215747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Fri Aug 15 13:42:15 2014
@@ -441,7 +441,7 @@ bool AMDGPUTargetLowering::isLoadBitCast
bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
assert(VT.isFloatingPoint());
- return VT == MVT::f32;
+ return VT == MVT::f32 || VT == MVT::f64;
}
bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=215747&r1=215746&r2=215747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Fri Aug 15 13:42:15 2014
@@ -226,7 +226,6 @@ SITargetLowering::SITargetLowering(Targe
// FIXME: These should be removed and handled the same was as f32 fneg. Source
// modifiers also work for the double instructions.
setOperationAction(ISD::FNEG, MVT::f64, Expand);
- setOperationAction(ISD::FABS, MVT::f64, Expand);
setOperationAction(ISD::FDIV, MVT::f32, Custom);
@@ -665,6 +664,35 @@ MachineBasicBlock * SITargetLowering::Em
MI->eraseFromParent();
break;
}
+ case AMDGPU::FABS64_SI: {
+ MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
+ const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
+ getTargetMachine().getSubtargetImpl()->getInstrInfo());
+
+ DebugLoc DL = MI->getDebugLoc();
+ unsigned SuperReg = MI->getOperand(0).getReg();
+ unsigned SrcReg = MI->getOperand(1).getReg();
+
+ unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
+
+ // Copy the subregister to make sure it is the right register class.
+ unsigned VReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
+ BuildMI(*BB, I, DL, TII->get(AMDGPU::COPY), VReg)
+ .addReg(SrcReg, 0, AMDGPU::sub1);
+
+ // We only need to mask the upper half of the register pair.
+ BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), TmpReg)
+ .addImm(0x7fffffff)
+ .addReg(VReg);
+
+ BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
+ .addReg(SrcReg, 0, AMDGPU::sub0)
+ .addImm(AMDGPU::sub0)
+ .addReg(TmpReg)
+ .addImm(AMDGPU::sub1);
+ MI->eraseFromParent();
+ break;
+ }
case AMDGPU::FNEG_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
Added: llvm/trunk/test/CodeGen/R600/fabs.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fabs.f64.ll?rev=215747&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fabs.f64.ll (added)
+++ llvm/trunk/test/CodeGen/R600/fabs.f64.ll Fri Aug 15 13:42:15 2014
@@ -0,0 +1,97 @@
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+
+declare i32 @llvm.r600.read.tidig.x() nounwind readnone
+
+declare double @fabs(double) readnone
+declare double @llvm.fabs.f64(double) readnone
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
+declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
+
+; FUNC-LABEL: @v_fabs_f64
+; SI: V_AND_B32
+; SI: S_ENDPGM
+define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
+ %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
+ %tidext = sext i32 %tid to i64
+ %gep = getelementptr double addrspace(1)* %in, i64 %tidext
+ %val = load double addrspace(1)* %gep, align 8
+ %fabs = call double @llvm.fabs.f64(double %val)
+ store double %fabs, double addrspace(1)* %out
+ ret void
+}
+
+; FUNC-LABEL: @fabs_f64
+; SI: V_AND_B32
+; SI-NOT: V_AND_B32
+; SI: S_ENDPGM
+define void @fabs_f64(double addrspace(1)* %out, double %in) {
+ %fabs = call double @llvm.fabs.f64(double %in)
+ store double %fabs, double addrspace(1)* %out
+ ret void
+}
+
+; FUNC-LABEL: @fabs_v2f64
+; SI: V_AND_B32
+; SI: V_AND_B32
+; SI: S_ENDPGM
+define void @fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
+ %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
+ store <2 x double> %fabs, <2 x double> addrspace(1)* %out
+ ret void
+}
+
+; FUNC-LABEL: @fabs_v4f64
+; SI: V_AND_B32
+; SI: V_AND_B32
+; SI: V_AND_B32
+; SI: V_AND_B32
+; SI: S_ENDPGM
+define void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
+ %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
+ store <4 x double> %fabs, <4 x double> addrspace(1)* %out
+ ret void
+}
+
+; SI-LABEL: @fabs_fold_f64
+; SI: S_LOAD_DWORDX2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-NOT: AND
+; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
+; SI: S_ENDPGM
+define void @fabs_fold_f64(double addrspace(1)* %out, double %in0, double %in1) {
+ %fabs = call double @llvm.fabs.f64(double %in0)
+ %fmul = fmul double %fabs, %in1
+ store double %fmul, double addrspace(1)* %out
+ ret void
+}
+
+; SI-LABEL: @fabs_fn_fold_f64
+; SI: S_LOAD_DWORDX2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-NOT: AND
+; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
+; SI: S_ENDPGM
+define void @fabs_fn_fold_f64(double addrspace(1)* %out, double %in0, double %in1) {
+ %fabs = call double @fabs(double %in0)
+ %fmul = fmul double %fabs, %in1
+ store double %fmul, double addrspace(1)* %out
+ ret void
+}
+
+; FUNC-LABEL: @fabs_free_f64
+; SI: V_AND_B32
+; SI: S_ENDPGM
+define void @fabs_free_f64(double addrspace(1)* %out, i64 %in) {
+ %bc= bitcast i64 %in to double
+ %fabs = call double @llvm.fabs.f64(double %bc)
+ store double %fabs, double addrspace(1)* %out
+ ret void
+}
+
+; FUNC-LABEL: @fabs_fn_free_f64
+; SI: V_AND_B32
+; SI: S_ENDPGM
+define void @fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
+ %bc= bitcast i64 %in to double
+ %fabs = call double @fabs(double %bc)
+ store double %fabs, double addrspace(1)* %out
+ ret void
+}
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