[PATCH][AVX512] FMA masking instruction variants and intrinsics

[Demikhovsky, Elena]

About 0002 patch.

How many operands X86ISD::VALIGN node may accept? I suggest to distinguish between masked and non-masked SDNode.
You can add X86ISD::VALIGNM, for example.

I also think that you should check the mask operand for "-1" constant value.
In this case copying -1 to GR and from GR to mask register is redundant.

-  Elena


-----Original Message-----
From: Adam Nemet [mailto:anemet at apple.com] 
Sent: Tuesday, August 12, 2014 23:36
To: Demikhovsky, Elena; Robert Khasanov
Cc: llvm-commits
Subject: [PATCH][AVX512] FMA masking instruction variants and intrinsics

Hi,

Elena made the comment regarding the FMA intrinsics earlier to try to only expose the masking versions as intrinsics rather than having two sets of the intrinsics (masking, unconditional: with an all-one mask).  These changes implement that.

The flow of the patchset is to first adjust the masking base class to accommodate the FMA instruction and then add the variants.  We also need to rename the existing intrinsics to masking and provide the lowering.

Along the way there are some cleanup and refactoring patches as well.  Hopefully this should be clear from the log in the individual patch files.

As the last patch, I've included the intrinsic header diff I am planning to commit in CFE.  I followed the existing precedence set by AVX to use the LLVM intrinsic for nmadd rather than negate the first operand and fall back on the madd intrinsic.  We can also change that later if that seems more appropriate assuming of course that codegen will recover the nmadd.

Thanks and please let me know if it looks good.

Adam
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