[llvm] r215270 - R600/SI: Custom lower CONCAT_VECTORS
Tom Stellard
thomas.stellard at amd.com
Fri Aug 8 18:06:56 PDT 2014
Author: tstellar
Date: Fri Aug 8 20:06:56 2014
New Revision: 215270
URL: http://llvm.org/viewvc/llvm-project?rev=215270&view=rev
Log:
R600/SI: Custom lower CONCAT_VECTORS
This will lower them using register copies rather than loads and stores
to the stack.
Modified:
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
llvm/trunk/test/CodeGen/R600/concat_vectors.ll
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=215270&r1=215269&r2=215270&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Fri Aug 8 20:06:56 2014
@@ -196,10 +196,12 @@ SITargetLowering::SITargetLowering(Targe
case ISD::BITCAST:
case ISD::EXTRACT_VECTOR_ELT:
case ISD::INSERT_VECTOR_ELT:
- case ISD::CONCAT_VECTORS:
case ISD::INSERT_SUBVECTOR:
case ISD::EXTRACT_SUBVECTOR:
break;
+ case ISD::CONCAT_VECTORS:
+ setOperationAction(Op, VT, Custom);
+ break;
default:
setOperationAction(Op, VT, Expand);
break;
Modified: llvm/trunk/test/CodeGen/R600/concat_vectors.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/concat_vectors.ll?rev=215270&r1=215269&r2=215270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/concat_vectors.ll (original)
+++ llvm/trunk/test/CodeGen/R600/concat_vectors.ll Fri Aug 8 20:06:56 2014
@@ -77,8 +77,7 @@ define void @test_concat_v4f32(<8 x floa
}
; FUNC-LABEL: @test_concat_v8f32
-; FIXME: This is currently being expanded with loads / stores to the stack.
-; FIXME-SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000
+; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000
; SI-NOT: MOVREL
define void @test_concat_v8f32(<16 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
%concat = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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