Author: anemet
Date: Thu Aug 7 18:18:18 2014
New Revision: 215168
URL: http://llvm.org/viewvc/llvm-project?rev=215168&view=rev
Log:
[AVX512] Add codegen test for the masking variant of valign
The AddedComplexity is needed just like in avx512_perm_3src. There may be a
bug in the complexity computation...
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=215168&r1=215167&r2=215168&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu Aug 7 18:18:18 2014
@@ -8,8 +8,9 @@ multiclass AVX512_masking<bits<8> O, For
"$dst, "#IntelSrcAsm#"}",
[(set RC:$dst, RHS)]>;
- let Constraints = "$src0 = $dst" in
- def NAME#k: AVX512<O, F, Outs,
+ // Prefer over VMOV*rrk Pat<>
+ let Constraints = "$src0 = $dst", AddedComplexity = 20 in
+ def NAME#k: AVX512<O, F, Outs,
!con((ins RC:$src0, KRC:$mask), Ins),
OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
"$dst {${mask}}, "#IntelSrcAsm#"}",
Modified: llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll?rev=215168&r1=215167&r2=215168&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll Thu Aug 7 18:18:18 2014
@@ -207,6 +207,15 @@ define <8 x double> @test16(<8 x double>
ret <8 x double> %c
}
+; CHECK-LABEL: test16k
+; CHECK: valignq $2, %zmm0, %zmm1, %zmm2 {%k1} #
+define <8 x i64> @test16k(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) nounwind {
+ %c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
+ %m = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> %src
+ ret <8 x i64> %res
+}
+
; CHECK-LABEL: test17
; CHECK: vshufpd $19, %zmm1, %zmm0
; CHECK: ret