[PATCH] [X86] Allow atomic operations using immediates to avoid using a register

[Philip Reames]

This version LGTM pending review by someone on the backend elements.

Note: I think your refinement of the tests may have pointed out a related bug w.r.t. the missing lock prefix on sequentially consistent accesses.  If so, I'm fine with addressing that separately.

================
Comment at: test/CodeGen/X86/atomic_mi.ll:223
@@ +222,3 @@
+; X32-LABEL: and_32_seq_cst
+; X32: xchgl
+  %1 = load atomic i32* %p monotonic, align 4
----------------
Shouldn't there be a lock prefix on this one to enforce the StoreLoad barrier required by cst?  cst is w.r.t. all addresses (unlike every other ordering mode...)

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Comment at: test/CodeGen/X86/atomic_mi.ll:293
@@ +292,3 @@
+  %2 = or i32 %1, 2
+  store atomic i32 %2, i32* %p seq_cst, align 4
+  ret void
----------------
Same here.

================
Comment at: test/CodeGen/X86/atomic_mi.ll:357
@@ +356,3 @@
+; X32-LABEL: xor_32_seq_cst
+; X32: xchgl
+  %1 = load atomic i32* %p monotonic, align 4
----------------
Again, lock prefix?

http://reviews.llvm.org/D4796