[llvm] r215102 - Add first bunch of SPE instructions. As they overlap with Altivec, mark
Joerg Sonnenberger
joerg at bec.de
Thu Aug 7 05:18:21 PDT 2014
Author: joerg
Date: Thu Aug 7 07:18:21 2014
New Revision: 215102
URL: http://llvm.org/viewvc/llvm-project?rev=215102&view=rev
Log:
Add first bunch of SPE instructions. As they overlap with Altivec, mark
them as parser-only until the disassembler is extended to handle
predicates properly.
Added:
llvm/trunk/lib/Target/PowerPC/PPCInstrSPE.td
llvm/trunk/test/MC/PowerPC/ppc64-encoding-spe.s
Modified:
llvm/trunk/lib/Target/PowerPC/PPC.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
Modified: llvm/trunk/lib/Target/PowerPC/PPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.td?rev=215102&r1=215101&r2=215102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.td Thu Aug 7 07:18:21 2014
@@ -56,6 +56,8 @@ def FeatureCRBits : SubtargetFeature<
"Use condition-register bits individually">;
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
"Enable Altivec instructions">;
+def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
+ "Enable SPE instructions">;
def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
"Enable the MFOCRF instruction">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=215102&r1=215101&r2=215102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Aug 7 07:18:21 2014
@@ -632,6 +632,7 @@ def IsNotBookE : Predicate<"!PPCSubTarg
def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
def IsE500 : Predicate<"PPCSubTarget->isE500()">;
+def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
//===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions.
@@ -2521,6 +2522,7 @@ def : Pat<(fcopysign f32:$frB, f64:$frA)
(FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
include "PPCInstrAltivec.td"
+include "PPCInstrSPE.td"
include "PPCInstr64Bit.td"
include "PPCInstrVSX.td"
@@ -3325,6 +3327,9 @@ def : InstAlias<"mfdear $Rx", (MFSPR gpr
def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
+def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
+def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
+
def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
@@ -3637,4 +3642,3 @@ defm : TrapExtendedMnemonic<"lgt", 1>;
defm : TrapExtendedMnemonic<"lnl", 5>;
defm : TrapExtendedMnemonic<"lng", 6>;
defm : TrapExtendedMnemonic<"u", 31>;
-
Added: llvm/trunk/lib/Target/PowerPC/PPCInstrSPE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrSPE.td?rev=215102&view=auto
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrSPE.td (added)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrSPE.td Thu Aug 7 07:18:21 2014
@@ -0,0 +1,68 @@
+//=======-- PPCInstrSPE.td - The PowerPC SPE Extension -*- tablegen -*-=======//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Signal Processing Engine extension to
+// the PowerPC instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> {
+ bits<5> RT;
+ bits<5> RA;
+ bits<5> RB;
+
+ let Pattern = [];
+
+ let Inst{6-10} = RT;
+ let Inst{11-15} = RA;
+ let Inst{16-20} = RB;
+ let Inst{21-31} = xo;
+}
+
+let Predicates = [HasSPE], isAsmParserOnly = 1 in {
+
+def EVMRA : EVXForm_1<1220, (outs gprc:$RT), (ins gprc:$RA),
+ "evmra $RT, $RA", IIC_VecFP> {
+ let RB = 0;
+}
+
+def EVLDDX : EVXForm_1<768, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlddx $RT, $RA, $RB", IIC_VecFP>;
+def EVLDWX : EVXForm_1<770, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evldwx $RT, $RA, $RB", IIC_VecFP>;
+def EVLDHX : EVXForm_1<772, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evldhx $RT, $RA, $RB", IIC_VecFP>;
+def EVLHHESPLATX : EVXForm_1<776, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlhhesplatx $RT, $RA, $RB", IIC_VecFP>;
+def EVLHHOUSPLATX : EVXForm_1<780, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlhhousplatx $RT, $RA, $RB", IIC_VecFP>;
+def EVLHHOSSPLATX : EVXForm_1<782, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlhhossplatx $RT, $RA, $RB", IIC_VecFP>;
+def EVLWHEX : EVXForm_1<784, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlwhex $RT, $RA, $RB", IIC_VecFP>;
+def EVLWHOUX : EVXForm_1<788, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlwhoux $RT, $RA, $RB", IIC_VecFP>;
+def EVLWHOSX : EVXForm_1<790, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlwhosx $RT, $RA, $RB", IIC_VecFP>;
+def EVLWWSPLATX : EVXForm_1<792, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlwwsplatx $RT, $RA, $RB", IIC_VecFP>;
+def EVLWHSPLATX : EVXForm_1<796, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evlwhsplatx $RT, $RA, $RB", IIC_VecFP>;
+
+def EVMERGEHI : EVXForm_1<556, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evmergehi $RT, $RA, $RB", IIC_VecFP>;
+def EVMERGELO : EVXForm_1<557, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evmergelo $RT, $RA, $RB", IIC_VecFP>;
+def EVMERGEHILO : EVXForm_1<558, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evmergehilo $RT, $RA, $RB", IIC_VecFP>;
+def EVMERGELOHI : EVXForm_1<559, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "evmergelohi $RT, $RA, $RB", IIC_VecFP>;
+
+} // HasSPE
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=215102&r1=215101&r2=215102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Aug 7 07:18:21 2014
@@ -119,6 +119,7 @@ void PPCSubtarget::initializeEnvironment
Use64BitRegs = false;
UseCRBits = false;
HasAltivec = false;
+ HasSPE = false;
HasQPX = false;
HasVSX = false;
HasFCPSGN = false;
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=215102&r1=215101&r2=215102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Thu Aug 7 07:18:21 2014
@@ -83,6 +83,7 @@ protected:
bool UseCRBits;
bool IsPPC64;
bool HasAltivec;
+ bool HasSPE;
bool HasQPX;
bool HasVSX;
bool HasFCPSGN;
@@ -225,6 +226,7 @@ public:
bool hasFPRND() const { return HasFPRND; }
bool hasFPCVT() const { return HasFPCVT; }
bool hasAltivec() const { return HasAltivec; }
+ bool hasSPE() const { return HasSPE; }
bool hasQPX() const { return HasQPX; }
bool hasVSX() const { return HasVSX; }
bool hasMFOCRF() const { return HasMFOCRF; }
Added: llvm/trunk/test/MC/PowerPC/ppc64-encoding-spe.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-spe.s?rev=215102&view=auto
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-spe.s (added)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-spe.s Thu Aug 7 07:18:21 2014
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
+
+# Instructions from the Signal Processing Engine extension:
+
+# CHECK-BE: evlddx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x00]
+# CHECK-LE: evlddx 14, 21, 28 # encoding: [0x00,0xe3,0xd5,0x11]
+evlddx %r14, %r21, %r28
+# CHECK-BE: evldwx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x02]
+# CHECK-LE: evldwx 14, 21, 28 # encoding: [0x02,0xe3,0xd5,0x11]
+evldwx %r14, %r21, %r28
+# CHECK-BE: evldhx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x04]
+# CHECK-LE: evldhx 14, 21, 28 # encoding: [0x04,0xe3,0xd5,0x11]
+evldhx %r14, %r21, %r28
+# CHECK-BE: evlhhesplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x08]
+# CHECK-LE: evlhhesplatx 14, 21, 28 # encoding: [0x08,0xe3,0xd5,0x11]
+evlhhesplatx %r14, %r21, %r28
+# CHECK-BE: evlhhousplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x0c]
+# CHECK-LE: evlhhousplatx 14, 21, 28 # encoding: [0x0c,0xe3,0xd5,0x11]
+evlhhousplatx %r14, %r21, %r28
+# CHECK-BE: evlhhossplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x0e]
+# CHECK-LE: evlhhossplatx 14, 21, 28 # encoding: [0x0e,0xe3,0xd5,0x11]
+evlhhossplatx %r14, %r21, %r28
+# CHECK-BE: evlwhex 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x10]
+# CHECK-LE: evlwhex 14, 21, 28 # encoding: [0x10,0xe3,0xd5,0x11]
+evlwhex %r14, %r21, %r28
+# CHECK-BE: evlwhoux 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x14]
+# CHECK-LE: evlwhoux 14, 21, 28 # encoding: [0x14,0xe3,0xd5,0x11]
+evlwhoux %r14, %r21, %r28
+# CHECK-BE: evlwhosx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x16]
+# CHECK-LE: evlwhosx 14, 21, 28 # encoding: [0x16,0xe3,0xd5,0x11]
+evlwhosx %r14, %r21, %r28
+# CHECK-BE: evlwwsplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x18]
+# CHECK-LE: evlwwsplatx 14, 21, 28 # encoding: [0x18,0xe3,0xd5,0x11]
+evlwwsplatx %r14, %r21, %r28
+# CHECK-BE: evlwhsplatx 14, 21, 28 # encoding: [0x11,0xd5,0xe3,0x1c]
+# CHECK-LE: evlwhsplatx 14, 21, 28 # encoding: [0x1c,0xe3,0xd5,0x11]
+evlwhsplatx %r14, %r21, %r28
+# CHECK-BE: evmergehi 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2c]
+# CHECK-LE: evmergehi 14, 21, 28 # encoding: [0x2c,0xe2,0xd5,0x11]
+evmergehi %r14, %r21, %r28
+# CHECK-BE: evmergelo 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2d]
+# CHECK-LE: evmergelo 14, 21, 28 # encoding: [0x2d,0xe2,0xd5,0x11]
+evmergelo %r14, %r21, %r28
+# CHECK-BE: evmergehilo 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2e]
+# CHECK-LE: evmergehilo 14, 21, 28 # encoding: [0x2e,0xe2,0xd5,0x11]
+evmergehilo %r14, %r21, %r28
+# CHECK-BE: evmergelohi 14, 21, 28 # encoding: [0x11,0xd5,0xe2,0x2f]
+# CHECK-LE: evmergelohi 14, 21, 28 # encoding: [0x2f,0xe2,0xd5,0x11]
+evmergelohi %r14, %r21, %r28
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