[llvm] r214716 - [PowerPC] MULHU/MULHS are not legal for vector types

[Ulrich Weigand]

Author: uweigand
Date: Mon Aug  4 08:27:12 2014
New Revision: 214716

URL: http://llvm.org/viewvc/llvm-project?rev=214716&view=rev
Log:
[PowerPC] MULHU/MULHS are not legal for vector types

I ran into some test failures where common code changed vector division
by constant into a multiply-high operation (MULHU).  But these are not
implemented by the back-end, so we failed to recognize the insn.

Fixed by marking MULHU/MULHS as Expand for vector types.


Added:
    llvm/trunk/test/CodeGen/PowerPC/vec_urem_const.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=214716&r1=214715&r2=214716&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug  4 08:27:12 2014
@@ -453,6 +453,8 @@ PPCTargetLowering::PPCTargetLowering(PPC
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
       setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
       setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
+      setOperationAction(ISD::MULHU, VT, Expand);
+      setOperationAction(ISD::MULHS, VT, Expand);
       setOperationAction(ISD::UMUL_LOHI, VT, Expand);
       setOperationAction(ISD::SMUL_LOHI, VT, Expand);
       setOperationAction(ISD::UDIVREM, VT, Expand);

Added: llvm/trunk/test/CodeGen/PowerPC/vec_urem_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_urem_const.ll?rev=214716&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_urem_const.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_urem_const.ll Mon Aug  4 08:27:12 2014
@@ -0,0 +1,10 @@
+; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s
+
+; Common code used to replace the urem by a mulhu, and compilation would
+; then crash since mulhu isn't supported on vector types.
+
+define <4 x i32> @test(<4 x i32> %x) {
+entry:
+  %0 = urem <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+  ret <4 x i32> %0
+}