[llvm] r214634 - [AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available.
James Molloy
james.molloy at arm.com
Sat Aug 2 10:24:20 PDT 2014
Hi Renato,
I've updated the triple in r214637.
Cheers,
James
-----Original Message-----
From: Renato Golin [mailto:renato.golin at linaro.org]
Sent: 02 August 2014 18:20
To: Tim Northover
Cc: James Molloy; LLVM Commits
Subject: Re: [llvm] r214634 - [AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available.
On 2 August 2014 17:49, Tim Northover <t.p.northover at gmail.com> wrote:
> It's mostly irrelevant either way. Both are tested (probably rightly);
> any eventual change will need a massive "sed s//" anyway; and in the
> meantime they should behave the same.
Changes, yes, but adding new ones?
--renato
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