[llvm] r214608 - R600/SI: Fix formatting.

[Matt Arsenault]

Author: arsenm
Date: Fri Aug  1 20:10:28 2014
New Revision: 214608

URL: http://llvm.org/viewvc/llvm-project?rev=214608&view=rev
Log:
R600/SI: Fix formatting.

Avoid weird line wrapping of BuildMI dest register.

Modified:
    llvm/trunk/lib/Target/R600/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=214608&r1=214607&r2=214608&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Fri Aug  1 20:10:28 2014
@@ -587,14 +587,16 @@ MachineBasicBlock * SITargetLowering::Em
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
     const SIInstrInfo *TII =
       static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
+
+    DebugLoc DL = MI->getDebugLoc();
+    unsigned DestReg = MI->getOperand(0).getReg();
     unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
-            Reg)
-            .addImm(0x7fffffff);
-    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
-            MI->getOperand(0).getReg())
-            .addReg(MI->getOperand(1).getReg())
-            .addReg(Reg);
+
+    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
+      .addImm(0x7fffffff);
+    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
+      .addReg(MI->getOperand(1).getReg())
+      .addReg(Reg);
     MI->eraseFromParent();
     break;
   }
@@ -602,28 +604,32 @@ MachineBasicBlock * SITargetLowering::Em
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
     const SIInstrInfo *TII =
       static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
+
+    DebugLoc DL = MI->getDebugLoc();
+    unsigned DestReg = MI->getOperand(0).getReg();
     unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
-            Reg)
-            .addImm(0x80000000);
-    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
-            MI->getOperand(0).getReg())
-            .addReg(MI->getOperand(1).getReg())
-            .addReg(Reg);
+
+    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
+      .addImm(0x80000000);
+    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
+      .addReg(MI->getOperand(1).getReg())
+      .addReg(Reg);
     MI->eraseFromParent();
     break;
   }
   case AMDGPU::FCLAMP_SI: {
     const SIInstrInfo *TII =
       static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
-    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
-            MI->getOperand(0).getReg())
-            .addImm(0) // SRC0 modifiers
-            .addOperand(MI->getOperand(1))
-            .addImm(0) // SRC1 modifiers
-            .addImm(0) // SRC1
-            .addImm(1) // CLAMP
-            .addImm(0); // OMOD
+
+    DebugLoc DL = MI->getDebugLoc();
+    unsigned DestReg = MI->getOperand(0).getReg();
+    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
+      .addImm(0) // SRC0 modifiers
+      .addOperand(MI->getOperand(1))
+      .addImm(0) // SRC1 modifiers
+      .addImm(0) // SRC1
+      .addImm(1) // CLAMP
+      .addImm(0); // OMOD
     MI->eraseFromParent();
   }
   }