[PATCH 1/1] R600: Modernize work item intrinsics test
Matt Arsenault
Matthew.Arsenault at amd.com
Thu Jul 31 14:56:57 PDT 2014
On 07/31/2014 02:53 PM, Jan Vesely wrote:
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
>
> This is a preparation before adding workdim intrinsics test.
>
> test/CodeGen/R600/work-item-intrinsics.ll | 163 +++++++++++++++---------------
> 1 file changed, 82 insertions(+), 81 deletions(-)
>
> diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll
> index 0123659..4e3908b 100644
> --- a/test/CodeGen/R600/work-item-intrinsics.ll
> +++ b/test/CodeGen/R600/work-item-intrinsics.ll
> @@ -1,13 +1,14 @@
> -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
> -; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
> -
> -; R600-CHECK: @ngroups_x
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[0].X
> -; SI-CHECK: @ngroups_x
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
2 minor issues, other than that LGTM:
-check-prefix usually uses 1 dash
> +
> +
> +; FUNC: @ngroups_x
These should be FUNC-LABEL
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[0].X
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @ngroups_x (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.ngroups.x() #0
> @@ -15,13 +16,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @ngroups_y
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[0].Y
> -; SI-CHECK: @ngroups_y
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x1
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @ngroups_y
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[0].Y
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x1
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @ngroups_y (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.ngroups.y() #0
> @@ -29,13 +30,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @ngroups_z
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[0].Z
> -; SI-CHECK: @ngroups_z
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x2
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @ngroups_z
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[0].Z
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x2
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @ngroups_z (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.ngroups.z() #0
> @@ -43,13 +44,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @global_size_x
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[0].W
> -; SI-CHECK: @global_size_x
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x3
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @global_size_x
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[0].W
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x3
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @global_size_x (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.global.size.x() #0
> @@ -57,13 +58,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @global_size_y
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[1].X
> -; SI-CHECK: @global_size_y
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x4
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @global_size_y
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[1].X
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x4
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @global_size_y (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.global.size.y() #0
> @@ -71,13 +72,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @global_size_z
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[1].Y
> -; SI-CHECK: @global_size_z
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x5
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @global_size_z
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[1].Y
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x5
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @global_size_z (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.global.size.z() #0
> @@ -85,13 +86,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @local_size_x
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[1].Z
> -; SI-CHECK: @local_size_x
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x6
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @local_size_x
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[1].Z
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x6
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @local_size_x (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.local.size.x() #0
> @@ -99,13 +100,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @local_size_y
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[1].W
> -; SI-CHECK: @local_size_y
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x7
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @local_size_y
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[1].W
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x7
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @local_size_y (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.local.size.y() #0
> @@ -113,13 +114,13 @@ entry:
> ret void
> }
>
> -; R600-CHECK: @local_size_z
> -; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> -; R600-CHECK: MOV [[VAL]], KC0[2].X
> -; SI-CHECK: @local_size_z
> -; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x8
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @local_size_z
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[2].X
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x8
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @local_size_z (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.local.size.z() #0
> @@ -131,9 +132,9 @@ entry:
> ; Currently we always use exactly 2 user sgprs for the pointer to the
> ; kernel arguments, but this may change in the future.
>
> -; SI-CHECK: @tgid_x
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s4
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @tgid_x
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s4
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @tgid_x (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.tgid.x() #0
> @@ -141,9 +142,9 @@ entry:
> ret void
> }
>
> -; SI-CHECK: @tgid_y
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s5
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @tgid_y
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s5
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @tgid_y (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.tgid.y() #0
> @@ -151,9 +152,9 @@ entry:
> ret void
> }
>
> -; SI-CHECK: @tgid_z
> -; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s6
> -; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
> +; FUNC: @tgid_z
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s6
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> define void @tgid_z (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.tgid.z() #0
> @@ -161,8 +162,8 @@ entry:
> ret void
> }
>
> -; SI-CHECK: @tidig_x
> -; SI-CHECK: BUFFER_STORE_DWORD v0
> +; FUNC: @tidig_x
> +; SI: BUFFER_STORE_DWORD v0
> define void @tidig_x (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.tidig.x() #0
> @@ -170,8 +171,8 @@ entry:
> ret void
> }
>
> -; SI-CHECK: @tidig_y
> -; SI-CHECK: BUFFER_STORE_DWORD v1
> +; FUNC: @tidig_y
> +; SI: BUFFER_STORE_DWORD v1
> define void @tidig_y (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.tidig.y() #0
> @@ -179,8 +180,8 @@ entry:
> ret void
> }
>
> -; SI-CHECK: @tidig_z
> -; SI-CHECK: BUFFER_STORE_DWORD v2
> +; FUNC: @tidig_z
> +; SI: BUFFER_STORE_DWORD v2
> define void @tidig_z (i32 addrspace(1)* %out) {
> entry:
> %0 = call i32 @llvm.r600.read.tidig.z() #0
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