[PATCH] Add isRegSequence property

[Quentin Colombet]

Hi hfinkel,

Hi,

This patch adds a new property: isRegSequence and the related target hook: TargetIntrInfo::getRegSequenceInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE.

I am looking forward for your feedbacks!

** Context **

This patch is a follow-up of the copy rewriting work made in peephole (http://reviews.llvm.org/D4086), which landed in r212100.

This patch is the first of a set of three patches that would teach how to get rid of some target specific copy in the advanced copy optimization of the peephole optimizer. See http://reviews.llvm.org/D4086 for more details.

Thanks to the property introduced in this patch, we would be able to optimize the following sequence:
_simpleVectorDiv:                       @ @simpleVectorDiv
@ BB#0:                                 @ %entry
	vmov	d0, r2, r3
	vmov	d1, r0, r1
	vmov	r0, s0
	vmov	r1, s2
	udiv	r0, r1, r0
	vmov	r1, s1
	vmov	r2, s3
	udiv	r1, r2, r1
	vmov.32	d16[0], r0
	vmov.32	d16[1], r1
	vmov	r0, r1, d16
	bx	lr

into:
	udiv	r0, r0, r2
	udiv	r1, r1, r3
	vmov.32	d16[0], r0
	vmov.32	d16[1], r1
	vmov	r0, r1, d16
	bx	lr

But this is for the next patches (see next section).

** Proposed Patch **

The proposed patch allows to specify that an instruction behaves like a (kind of) REG_SEQUENCE.

In that case, "vmov d0, r2, r3" is equivalent to D0 = REG_SEQUENCE r2, ssub0, r3, ssub1.
The isRegSequence property is used to specify that, and the target hook TargetInstrInfo::getRegSequenceInputs is used to specify how to interpret those instructions if it was a REG_SEQUENCE.

The target hook takes a DefIdx because it is possible that an instruction behaves like a REG_SEQUENCE for a given definition, but not for another.

** What Is Next? **

- Make use of this property on target specific instruction {F119484}.
- Teach the advanced copy optimizer about those instructions {F119485}.
- Do the same for insert_subreg and extract_subreg.

As soon as this patch lands, the next ones would be available through llvm-review.
I am attaching them to show the global direction of this.

Thanks,
-Quentin

http://reviews.llvm.org/D4734

Files:
  include/llvm/CodeGen/MachineInstr.h
  include/llvm/MC/MCInstrDesc.h
  include/llvm/Target/TargetInstrInfo.h
  lib/CodeGen/TargetInstrInfo.cpp
  utils/TableGen/CodeGenInstruction.cpp
  utils/TableGen/CodeGenInstruction.h
  utils/TableGen/InstrInfoEmitter.cpp
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