[llvm] r214244 - Recognize BookE's mbar instruction.
Joerg Sonnenberger
joerg at bec.de
Tue Jul 29 16:16:31 PDT 2014
Author: joerg
Date: Tue Jul 29 18:16:31 2014
New Revision: 214244
URL: http://llvm.org/viewvc/llvm-project?rev=214244&view=rev
Log:
Recognize BookE's mbar instruction.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=214244&r1=214243&r2=214244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Tue Jul 29 18:16:31 2014
@@ -468,6 +468,15 @@ class XForm_sr<bits<6> opcode, bits<10>
let Inst{21-30} = xo;
}
+class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<5> MO;
+
+ let Inst{6-10} = MO;
+ let Inst{21-30} = xo;
+}
+
class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> {
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=214244&r1=214243&r2=214244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Jul 29 18:16:31 2014
@@ -3046,6 +3046,9 @@ def EIEIO : XForm_24_eieio<31, 854, (out
def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
"wait $L", IIC_LdStLoad, []>;
+def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
+ "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
+
def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
"mtsr $SR, $RS", IIC_SprMTSR>;
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt?rev=214244&r1=214243&r2=214244&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt Tue Jul 29 18:16:31 2014
@@ -33,6 +33,9 @@
# CHECK: wait 2
0x7c 0x40 0x00 0x7c
+# CHECK: mbar 1
+0x7c 0x20 0x06 0xac
+
# CHECK: dcbf 2, 3
0x7c 0x02 0x18 0xac
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s?rev=214244&r1=214243&r2=214244&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookII.s Tue Jul 29 18:16:31 2014
@@ -53,6 +53,9 @@
# CHECK-BE: wait 2 # encoding: [0x7c,0x40,0x00,0x7c]
# CHECK-LE: wait 2 # encoding: [0x7c,0x00,0x40,0x7c]
wait 2
+# CHECK-BE: mbar 1 # encoding: [0x7c,0x20,0x06,0xac]
+# CHECK-LE: mbar 1 # encoding: [0xac,0x06,0x20,0x7c]
+ mbar 1
# Extended mnemonics
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