[llvm] r214194 - R600/SI: Set bits on SMRD instructions

Matt Arsenault Matthew.Arsenault at amd.com
Tue Jul 29 11:51:54 PDT 2014


Author: arsenm
Date: Tue Jul 29 13:51:54 2014
New Revision: 214194

URL: http://llvm.org/viewvc/llvm-project?rev=214194&view=rev
Log:
R600/SI: Set bits on SMRD instructions

Set mayStore = 0 and enable named operand table.

Modified:
    llvm/trunk/lib/Target/R600/SIInstrFormats.td

Modified: llvm/trunk/lib/Target/R600/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=214194&r1=214193&r2=214194&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrFormats.td Tue Jul 29 13:51:54 2014
@@ -185,6 +185,9 @@ class SMRD <bits<5> op, bits<1> imm, dag
 
   let LGKM_CNT = 1;
   let SMRD = 1;
+  let mayStore = 0;
+  let mayLoad = 1;
+  let UseNamedOperandTable = 1;
 }
 
 //===----------------------------------------------------------------------===//





More information about the llvm-commits mailing list