[PATCH] R600/SI: Make argument loads invariant

[Tom Stellard]

On Sat, Jul 26, 2014 at 10:26:09PM +0000, Matt Arsenault wrote:
> http://reviews.llvm.org/D4685

LGTM.

> 
> Files:
>   lib/Target/R600/SIISelLowering.cpp
> 
> Index: lib/Target/R600/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/SIISelLowering.cpp
> +++ lib/Target/R600/SIISelLowering.cpp
> @@ -310,19 +310,27 @@
>  }
>  
>  SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
> -                                         SDLoc DL, SDValue Chain,
> +                                         SDLoc SL, SDValue Chain,
>                                           unsigned Offset, bool Signed) const {
> +  const DataLayout *DL = getDataLayout();
> +
> +  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
> +
>    MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
> -  PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
> -                                            AMDGPUAS::CONSTANT_ADDRESS);
> -  SDValue BasePtr =  DAG.getCopyFromReg(Chain, DL,
> +  PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
> +  SDValue BasePtr =  DAG.getCopyFromReg(Chain, SL,
>                             MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
> -  SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
> +  SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
>                                               DAG.getConstant(Offset, MVT::i64));
> -  return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
> -                            MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
> -                            false, false, MemVT.getSizeInBits() >> 3);
> -
> +  SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
> +  MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
> +
> +  return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
> +                     VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
> +                     false, // isVolatile
> +                     true, // isNonTemporal
> +                     true, // isInvariant
> +                     DL->getABITypeAlignment(Ty)); // Alignment
>  }
>  
>  SDValue SITargetLowering::LowerFormalArguments(

> Index: lib/Target/R600/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/SIISelLowering.cpp
> +++ lib/Target/R600/SIISelLowering.cpp
> @@ -310,19 +310,27 @@
>  }
>  
>  SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
> -                                         SDLoc DL, SDValue Chain,
> +                                         SDLoc SL, SDValue Chain,
>                                           unsigned Offset, bool Signed) const {
> +  const DataLayout *DL = getDataLayout();
> +
> +  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
> +
>    MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
> -  PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
> -                                            AMDGPUAS::CONSTANT_ADDRESS);
> -  SDValue BasePtr =  DAG.getCopyFromReg(Chain, DL,
> +  PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
> +  SDValue BasePtr =  DAG.getCopyFromReg(Chain, SL,
>                             MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
> -  SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
> +  SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
>                                               DAG.getConstant(Offset, MVT::i64));
> -  return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
> -                            MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
> -                            false, false, MemVT.getSizeInBits() >> 3);
> -
> +  SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
> +  MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
> +
> +  return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
> +                     VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
> +                     false, // isVolatile
> +                     true, // isNonTemporal
> +                     true, // isInvariant
> +                     DL->getABITypeAlignment(Ty)); // Alignment
>  }
>  
>  SDValue SITargetLowering::LowerFormalArguments(

> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits