[PATCH][AArch64] Prefer ldp x, x to ldr q

[James Molloy]

Hi,

Ping?

Cheers,

James


On 24 July 2014 17:23, James Molloy <james.molloy at arm.com> wrote:

> Hi Tim,
>
>
>
> “LDR Qn” instructions are no more performant (on any microarchitecture I
> know of) than “LDP Xm, Xn” or “LDP Dm, Dn”. In fact, there are no
> callee-saved Q registers so generating “LDR Qn” can cause serious
> performance problems, as it is immediately spilled.
>
>
>
> These are generated in two places – DAGCombine and SLP vectorize. Attached
> are two simple patches to disable these transformations for AArch64
> (actually if TLI->hasPairedLoad() which seems to have been made for this
> purpose).
>
>
>
> Are they OK?
>
>
>
> Cheers,
>
>
>
> James
>
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>
>
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