[llvm] r214043 - [x86] Sink a variable only used by asserts into the asserts. Should fix

Chandler Carruth chandlerc at gmail.com
Sat Jul 26 18:45:49 PDT 2014


Author: chandlerc
Date: Sat Jul 26 20:45:49 2014
New Revision: 214043

URL: http://llvm.org/viewvc/llvm-project?rev=214043&view=rev
Log:
[x86] Sink a variable only used by asserts into the asserts. Should fix
some -Werror bots, sorry for the noise.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=214043&r1=214042&r2=214043&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jul 26 20:45:49 2014
@@ -18871,9 +18871,9 @@ static bool combineX86ShufflesRecursivel
   if (VT.getSizeInBits() != 128)
     return false;
 
-  MVT RootVT = Root.getSimpleValueType();
-  assert(RootVT.isVector() && "Shuffles operate on vector types!");
-  assert(VT.getSizeInBits() == RootVT.getSizeInBits() &&
+  assert(Root.getSimpleValueType().isVector() &&
+         "Shuffles operate on vector types!");
+  assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
          "Can only combine shuffles of the same vector register size.");
 
   if (!isTargetShuffle(Op.getOpcode()))





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