[PATCH][AArch64] Prefer ldp x, x to ldr q

[James Molloy]

Hi Tim,

 

"LDR Qn" instructions are no more performant (on any microarchitecture I
know of) than "LDP Xm, Xn" or "LDP Dm, Dn". In fact, there are no
callee-saved Q registers so generating "LDR Qn" can cause serious
performance problems, as it is immediately spilled.

 

These are generated in two places - DAGCombine and SLP vectorize. Attached
are two simple patches to disable these transformations for AArch64
(actually if TLI->hasPairedLoad() which seems to have been made for this
purpose).

 

Are they OK?

 

Cheers,

 

James  
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140724/5efab479/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: qreg-dagcombine.diff
Type: application/octet-stream
Size: 1444 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140724/5efab479/attachment.obj>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: qreg-tti.diff
Type: application/octet-stream
Size: 1939 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140724/5efab479/attachment-0001.obj>