[llvm] r213809 - Reorganize and simplify local variables.

David Blaikie dblaikie at gmail.com
Wed Jul 23 15:44:28 PDT 2014


On Wed, Jul 23, 2014 at 3:27 PM, Eric Christopher <echristo at gmail.com> wrote:
> Author: echristo
> Date: Wed Jul 23 17:27:10 2014
> New Revision: 213809
>
> URL: http://llvm.org/viewvc/llvm-project?rev=213809&view=rev
> Log:
> Reorganize and simplify local variables.
>
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp?rev=213809&r1=213808&r2=213809&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp Wed Jul 23 17:27:10 2014
> @@ -40,19 +40,17 @@ static cl::opt<signed> RegPressureThresh
>    "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5),
>    cl::desc("Track reg pressure and switch priority to in-depth"));
>
> -
> -ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) :
> -  Picker(this),
> - InstrItins(IS->getTargetLowering()->getTargetMachine().getInstrItineraryData())
> -{
> -   TII = IS->getTargetLowering()->getTargetMachine().getInstrInfo();
> -   TRI = IS->getTargetLowering()->getTargetMachine().getRegisterInfo();
> -   TLI = IS->getTargetLowering();
> -
> -   const TargetMachine &tm = (*IS->MF).getTarget();
> -   ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,nullptr);
> -   // This hard requirement could be relaxed, but for now
> -   // do not let it procede.
> +ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS)
> +    : Picker(this),
> +      InstrItins(
> +          IS->getTargetLowering()->getTargetMachine().getInstrItineraryData()) {
> +  const TargetMachine &TM = (*IS->MF).getTarget();
> +  TRI = TM.getRegisterInfo();
> +  TLI = IS->getTargetLowering();
> +  TII = TM.getInstrInfo();

Any particular reason you reordered these (it was TII, TRI, TLI, now
it's TRI, TLI, TII)? If so, might be worth a comment to avoid anyone
falling into whatever issue you were addressing. If not, no worries.

- David

> +  ResourcesModel = TII->CreateTargetScheduleState(&TM, nullptr);
> +  // This hard requirement could be relaxed, but for now
> +  // do not let it procede.
>     assert (ResourcesModel && "Unimplemented CreateTargetScheduleState.");
>
>     unsigned NumRC = TRI->getNumRegClasses();
>
>
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