[llvm] r213773 - [NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled

[Justin Holewinski]

Bill, can you please merge this into the 3.5 release branch?

On Wed, 2014-07-23 at 10:40 -0700, Justin Holewinski wrote:
> Author: jholewinski
> Date: Wed Jul 23 12:40:45 2014
> New Revision: 213773
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=213773&view=rev
> Log:
> [NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled
> 
> With optimizations disabled, we disable the isel patterns for mul.wide; but we
> were still generating MULWIDE ISD nodes.  Now, we only try to generate MULWIDE
> ISD nodes in DAGCombine if the optimization level is not zero.
> 
> Modified:
>     llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
>     llvm/trunk/test/CodeGen/NVPTX/mulwide.ll
> 
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=213773&r1=213772&r2=213773&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Wed Jul 23 12:40:45 2014
> @@ -4213,8 +4213,7 @@ static SDValue PerformSHLCombine(SDNode
>  
>  SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
>                                                 DAGCombinerInfo &DCI) const {
> -  // FIXME: Get this from the DAG somehow
> -  CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
> +  CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
>    switch (N->getOpcode()) {
>      default: break;
>      case ISD::ADD:
> 
> Modified: llvm/trunk/test/CodeGen/NVPTX/mulwide.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/mulwide.ll?rev=213773&r1=213772&r2=213773&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/NVPTX/mulwide.ll (original)
> +++ llvm/trunk/test/CodeGen/NVPTX/mulwide.ll Wed Jul 23 12:40:45 2014
> @@ -1,35 +1,44 @@
> -; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
> +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O3 | FileCheck %s --check-prefix=OPT
> +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O0 | FileCheck %s --check-prefix=NOOPT
>  
> -; CHECK: mulwide16
> +; OPT-LABEL: @mulwide16
> +; NOOPT-LABEL: @mulwide16
>  define i32 @mulwide16(i16 %a, i16 %b) {
> -; CHECK: mul.wide.s16
> +; OPT: mul.wide.s16
> +; NOOPT: mul.lo.s32
>    %val0 = sext i16 %a to i32
>    %val1 = sext i16 %b to i32
>    %val2 = mul i32 %val0, %val1
>    ret i32 %val2
>  }
>  
> -; CHECK: mulwideu16
> +; OPT-LABEL: @mulwideu16
> +; NOOPT-LABEL: @mulwideu16
>  define i32 @mulwideu16(i16 %a, i16 %b) {
> -; CHECK: mul.wide.u16
> +; OPT: mul.wide.u16
> +; NOOPT: mul.lo.s32
>    %val0 = zext i16 %a to i32
>    %val1 = zext i16 %b to i32
>    %val2 = mul i32 %val0, %val1
>    ret i32 %val2
>  }
>  
> -; CHECK: mulwide32
> +; OPT-LABEL: @mulwide32
> +; NOOPT-LABEL: @mulwide32
>  define i64 @mulwide32(i32 %a, i32 %b) {
> -; CHECK: mul.wide.s32
> +; OPT: mul.wide.s32
> +; NOOPT: mul.lo.s64
>    %val0 = sext i32 %a to i64
>    %val1 = sext i32 %b to i64
>    %val2 = mul i64 %val0, %val1
>    ret i64 %val2
>  }
>  
> -; CHECK: mulwideu32
> +; OPT-LABEL: @mulwideu32
> +; NOOPT-LABEL: @mulwideu32
>  define i64 @mulwideu32(i32 %a, i32 %b) {
> -; CHECK: mul.wide.u32
> +; OPT: mul.wide.u32
> +; NOOPT: mul.lo.s64
>    %val0 = zext i32 %a to i64
>    %val1 = zext i32 %b to i64
>    %val2 = mul i64 %val0, %val1
> 
> 
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