[llvm] r213357 - R600: support f16 -> f64 conversion intrinsic.

[Tim Northover]

Author: tnorthover
Date: Fri Jul 18 03:43:24 2014
New Revision: 213357

URL: http://llvm.org/viewvc/llvm-project?rev=213357&view=rev
Log:
R600: support f16 -> f64 conversion intrinsic.

Unfortunately, we don't seem to have a direct truncation, but the
extension can be legally split into two operations so we should
support that.

Added:
    llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll
      - copied, changed from r213356, llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll
Removed:
    llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll
Modified:
    llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp

Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=213357&r1=213356&r2=213357&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Fri Jul 18 03:43:24 2014
@@ -242,6 +242,8 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
     setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
   }
 
+  setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
+
   const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
   for (MVT VT : ScalarIntVTs) {
     setOperationAction(ISD::SREM, VT, Expand);

Copied: llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll (from r213356, llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll?p2=llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll&p1=llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll&r1=213356&r2=213357&rev=213357&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll Fri Jul 18 03:43:24 2014
@@ -1,6 +1,7 @@
 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 
 declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
+declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
 
 ; SI-LABEL: @test_convert_fp16_to_fp32:
 ; SI: BUFFER_LOAD_USHORT [[VAL:v[0-9]+]]
@@ -12,3 +13,16 @@ define void @test_convert_fp16_to_fp32(f
   store float %cvt, float addrspace(1)* %out, align 4
   ret void
 }
+
+
+; SI-LABEL: @test_convert_fp16_to_fp64:
+; SI: BUFFER_LOAD_USHORT [[VAL:v[0-9]+]]
+; SI: V_CVT_F32_F16_e32 [[RESULT32:v[0-9]+]], [[VAL]]
+; SI: V_CVT_F64_F32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
+; SI: BUFFER_STORE_DWORDX2 [[RESULT]]
+define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
+  %val = load i16 addrspace(1)* %in, align 2
+  %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
+  store double %cvt, double addrspace(1)* %out, align 4
+  ret void
+}

Removed: llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll?rev=213356&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
-
-; SI-LABEL: @test_convert_fp16_to_fp32:
-; SI: BUFFER_LOAD_USHORT [[VAL:v[0-9]+]]
-; SI: V_CVT_F32_F16_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: BUFFER_STORE_DWORD [[RESULT]]
-define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
-  %val = load i16 addrspace(1)* %in, align 2
-  %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
-  store float %cvt, float addrspace(1)* %out, align 4
-  ret void
-}