[PATCH] Review for machine combiner pass

Gerolf Hoflehner ghoflehner at apple.com
Tue Jul 15 18:42:58 PDT 2014


+llvm-commits



Reminder/Background:


I implemented a pass for a late machine instruction combiner that may replace an instruction sequence by combined instruction(s) when it is beneficial to do so. It provides the infrastructure to evaluate instruction combining patterns like mul+add->madd based on machine trace information. Currently the DAG Combiner greedily generates combined instructions, which usually is a win for code size, but unfortunately can cause performance losses. To remedy this the new pass changes the logic from always generate combined instruction(s) to only do so when beneficial.


The design choice was driven by the desire to make it simple to a) add new pattern and b) add support for machine combining in a target. Consequently the combiner pass comes in 3 patches: First, the target independent driver that walks all instructions of a basic block, asks the target for possible combiner pattern, evaluates each pattern by having the target generate the instruction sequence represented by the pattern and finally replaces the old code  when the new sequence is more efficient. The pattern and the new code sequence are opaque to the driver. Second, the target dependent code which currently supports only AArch64: for a given instruction it records the possible combiner pattern and on demand generates the instruction sequence it represents. Third, optional dumps the critical path length for tuning support.


http://reviews.llvm.org/D4367


* Motivation + Example

The opportunity for this optimization is across the llvm test suite and benchmarks. 

Specific example: SingleSource/Benchmarks/Shootout/matrix (compiled with O3 flto for AArch64 gives a >20% gain):

Current assembly snippet:

0000000100007d24		mul      w6, w23, w6		// Chain of madds
0000000100007d28                madd    w5, w7, w5, w6		// All multiplies on critical path!
0000000100007d2c                ldp     w6, w7, [x4, #8]	
0000000100007d30                ldr     w23, [x11, x2]
0000000100007d34                madd    w5, w23, w6, w5
0000000100007d38                ldr     w6, [x12, x2]
0000000100007d3c                madd    w5, w6, w7, w5
0000000100007d40                ldr     w6, [x13, x2]
0000000100007d44                ldp     w7, w23, [x4, #16]
0000000100007d48                madd    w5, w6, w7, w5
0000000100007d4c                ldr     w6, [x14, x2]
0000000100007d50                madd    w5, w6, w23, w5
0000000100007d54                ldr     w6, [x15, x2]
0000000100007d58                ldp     w7, w23, [x4, #24]
0000000100007d5c                madd    w5, w6, w7, w5
0000000100007d60                ldr     w6, [x16, x2]
0000000100007d64                madd    w5, w6, w23, w5
0000000100007d68                ldr     w6, [x17, x2]
0000000100007d6c                ldp     w7, w23, [x4, #32]
0000000100007d70                ldr     w24, [x0, x2]
0000000100007d74                madd    w5, w6, w7, w5

				…
With machine combiner the multiplies can execute in parallel shortening the critical path (>20% gain):


0000000100007cf4                mul      w5, w7, w5		// Multiplies can execute in parallel
0000000100007cf8                ldp     w7, w23, [x4, #8]	// off critical path
0000000100007cfc                ldr     w24, [x10, x2]
0000000100007d00                mul      w6, w24, w6
0000000100007d04                ldr     w24, [x11, x2]
0000000100007d08                mul      w7, w24, w7
0000000100007d0c                ldr     w24, [x12, x2]
0000000100007d10                mul      w23, w24, w23
0000000100007d14                ldr     w24, [x13, x2]
0000000100007d18                add     w5, w6, w5
0000000100007d1c                ldp     w6, w25, [x4, #16]
0000000100007d20                mul      w6, w24, w6
0000000100007d24                ldr     w24, [x14, x2]
0000000100007d28                mul      w24, w24, w25
0000000100007d2c                ldr     w25, [x15, x2]
0000000100007d30                add     w5, w7, w5
0000000100007d34                ldp     w7, w26, [x4, #24]
0000000100007d38                mul      w7, w25, w7
0000000100007d3c                ldr     w25, [x16, x2]
0000000100007d40                mul      w25, w25, w26
0000000100007d44                ldr     w26, [x17, x2]
0000000100007d48                add     w5, w23, w5
0000000100007d4c                ldp     w23, w27, [x4, #32]
0000000100007d50                mul      w23, w26, w23
0000000100007d54                ldr     w26, [x0, x2]
0000000100007d58                mul      w26, w26, w27
0000000100007d5c                add     w5, w6, w5
								     ….


On Jul 15, 2014, at 6:26 PM, Gerolf Hoflehner <ghoflehner at apple.com> wrote:

> 
> Changes:
> 1) Added bool alwaysCombine() (Target/TargetInstrInfo.h) so targets
> can decide to always replace a given pattern. This should be equivalent to
> the current code in DAGCombine when a given pattern is disabled.
> 2) InstrDepth is now a small vector (MachineCombiner.cpp)
> 3) Added helper function instr2instrSC (MachineCombiner.cpp)
> 4) Improved comments as suggested by reviewers
> 
> http://reviews.llvm.org/D4367
> 
> Files:
>  include/llvm/CodeGen/MachineCombinerPattern.h
>  include/llvm/CodeGen/MachineTraceMetrics.h
>  include/llvm/CodeGen/Passes.h
>  include/llvm/CodeGen/TargetSchedule.h
>  include/llvm/InitializePasses.h
>  include/llvm/Target/TargetInstrInfo.h
>  lib/CodeGen/CMakeLists.txt
>  lib/CodeGen/CodeGen.cpp
>  lib/CodeGen/MachineCombiner.cpp
>  lib/CodeGen/MachineScheduler.cpp
>  lib/CodeGen/MachineTraceMetrics.cpp
>  lib/CodeGen/TargetSchedule.cpp
>  lib/Target/AArch64/AArch64InstrFormats.td
>  lib/Target/AArch64/AArch64InstrInfo.cpp
>  lib/Target/AArch64/AArch64InstrInfo.h
>  lib/Target/AArch64/AArch64TargetMachine.cpp
>  test/CodeGen/AArch64/aarch64-neon-mul-div.ll
>  test/CodeGen/AArch64/early-ifcvt.ll
> <D4367.11483.patch>

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