[PATCH] R600/SI: Fix select on i1

[Tom Stellard]

On Wed, Jul 09, 2014 at 09:41:15PM +0000, Matt Arsenault wrote:
> Also add some missing tests for operations on i1
> 

LGTM.

> http://reviews.llvm.org/D4442
> 
> Files:
>   lib/Target/R600/SIISelLowering.cpp
>   test/CodeGen/R600/and.ll
>   test/CodeGen/R600/or.ll
>   test/CodeGen/R600/select-i1.ll
>   test/CodeGen/R600/select.ll

> Index: lib/Target/R600/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/SIISelLowering.cpp
> +++ lib/Target/R600/SIISelLowering.cpp
> @@ -179,6 +179,9 @@
>      MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
>    };
>  
> +  setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
> +  setOperationAction(ISD::SELECT, MVT::i1, Promote);
> +
>    for (MVT VT : VecTypes) {
>      for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
>        switch(Op) {
> Index: test/CodeGen/R600/and.ll
> ===================================================================
> --- test/CodeGen/R600/and.ll
> +++ test/CodeGen/R600/and.ll
> @@ -80,6 +80,15 @@
>    ret void
>  }
>  
> +; FIXME: Should use SGPRs
> +; FUNC-LABEL: @s_and_i1
> +; SI: V_AND_B32
> +define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
> +  %and = and i1 %a, %b
> +  store i1 %and, i1 addrspace(1)* %out
> +  ret void
> +}
> +
>  ; FUNC-LABEL: @s_and_constant_i64
>  ; SI: S_AND_B64
>  define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
> Index: test/CodeGen/R600/or.ll
> ===================================================================
> --- test/CodeGen/R600/or.ll
> +++ test/CodeGen/R600/or.ll
> @@ -127,3 +127,19 @@
>    store i32 %trunc, i32 addrspace(1)* %out, align 8
>    ret void
>  }
> +
> +; EG-CHECK: @or_i1
> +; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
> +
> +; SI-CHECK: @or_i1
> +; SI-CHECK: S_OR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
> +define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
> +  %a = load float addrspace(1) * %in0
> +  %b = load float addrspace(1) * %in1
> +  %acmp = fcmp oge float %a, 0.000000e+00
> +  %bcmp = fcmp oge float %b, 0.000000e+00
> +  %or = or i1 %acmp, %bcmp
> +  %result = select i1 %or, float %a, float %b
> +  store float %result, float addrspace(1)* %out
> +  ret void
> +}
> Index: test/CodeGen/R600/select-i1.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/select-i1.ll
> @@ -0,0 +1,14 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +
> +; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI
> +
> +; FUNC-LABEL: @select_i1
> +; SI: V_CNDMASK_B32
> +; SI-NOT: V_CNDMASK_B32
> +define void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind {
> +  %cmp = icmp ugt i32 %cond, 5
> +  %sel = select i1 %cmp, i1 %a, i1 %b
> +  store i1 %sel, i1 addrspace(1)* %out, align 4
> +  ret void
> +}
> +
> Index: test/CodeGen/R600/select.ll
> ===================================================================
> --- test/CodeGen/R600/select.ll
> +++ test/CodeGen/R600/select.ll
> @@ -1,4 +1,5 @@
> -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
> +
>  
>  ; Normally icmp + select is optimized to select_cc, when this happens the
>  ; DAGLegalizer never sees the select and doesn't have a chance to leaglize it.
> @@ -6,13 +7,13 @@
>  ; In order to avoid the select_cc optimization, this test case calculates the
>  ; condition for the select in a separate basic block.
>  
> -; CHECK-LABEL: @select
> -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
> -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
> -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
> -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
> -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
> -; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
> +; FUNC-LABEL: @select
> +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
> +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
> +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
> +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
> +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
> +; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
>  define void @select (i32 addrspace(1)* %i32out, float addrspace(1)* %f32out,
>                       <2 x i32> addrspace(1)* %v2i32out, <2 x float> addrspace(1)* %v2f32out,
>                       <4 x i32> addrspace(1)* %v4i32out, <4 x float> addrspace(1)* %v4f32out,

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