[PATCH] PR18825 - New RegisterCoalescer subtarget hook

[David Peixotto]

Hi Chris,

It would be great to get this bug fixed. I have a general question about the heuristic.

I believe the case we need to avoid in the bug is quite rare (running out of registers), but the heuristic will prevent colaescing in other cases as well. Do you have any statistics for how many coalescings are prevented by the heuristic and any performance data for spec or llvm test suite?

Thanks,
David

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> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Chris Bieneman
> Sent: Friday, July 11, 2014 1:45 PM
> To: llvm-commits
> Subject: [PATCH] PR18825 - New RegisterCoalescer subtarget hook
> 
> The attached patch adds a new subtarget hook to the RegisterCoalescer, and
> an ARM implementation. The ARM implementation works around PR18825, and
> also better code in cases with a large number of NEON vectors in use.
> 
> The basic problem is that the coalescer is very aggressive at propagating
> constraints on the register classes, and the register allocator doesn’t
> know how to split sub-registers later to recover. This patch provides an
> escape valve for targets that encounter this problem to limit coalescing.
> 
> A few other notes about this patch:
> 
> (1) In code that triggers the heuristic (using a lot of large vector
> registers) this code can improve compile time substantially, and in other
> code it has no adverse impact.
> 
> (2) This code also breaks one of the tests in our test suite
> (CodeGen/ARM/vldm-sched-a9.ll). This test is designed to test NEON vector
> spilling, and with this patch the test no longer spills. With the final
> patch I will provide a new test case to test vector spilling, and this
> test will be marked XFAIL so that we don’t regress this and start spilling
> here again.
> 
> Thanks,
> -Chris