[PATCH] [AArch64] Generate tbz/tbnz when comparing against zero.

[Chad Rosier]

>>! In D4440#7, @xjwwm_cat wrote:
> I have tried your patch and test.Here, I doubt whether it has something to do with add/sub or adds/subs, and I have also tried some test case written by myself. 

The difference between add/sub and adds/subs is that the latter sets the NZCV bits.

>   void foo();
>   void gt(int tmp) {
>     if (tmp >= 0)
>       foo();
>   }
> 
> and the asm is below:
>     ge:                                     // @ge 
>   // BB#0:                                // %entry 
>           cmp      w0, #0                 // =0 
>           b.lt    .LBB1_2                           
>   // BB#1:                                // %if.then 
>           b       foo 
>   .LBB1_2:                                // %if.end 
>           ret 
>   .Ltmp3:
>         .size   ge, .Ltmp3-ge
> 
> I think the cmp and b.lt above can combine to tbz/tbnz. I think your patch should cover this case. When I chang the c code to (tmp>0), it generates 

AFAICT, that case can be handled by a similar combine, but it shouldn't block this patch.  Feel free to submit a patch of your own.

>   gt:                                     // @gt
>   // BB#0:                                // %entry
>          cmp      w0, #1                 // =1
>          b.lt    .LBB0_2
>   // BB#1:                                // %if.then
>          b       foo
>   .LBB0_2:                                // %if.end
>          ret
> I think this case may not be easy to generate TBZ/TBNZ, what is your opinion?

I don't think that this is possible as you're not strictly checking in sign bit.  You would need two checks, to see if the value is zero and another to check if it's negative.

> Thanks
> -David

 Chad

http://reviews.llvm.org/D4440