[llvm] r212708 - Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."

[NAKAMURA Takumi]

Author: chapuni
Date: Thu Jul 10 06:37:28 2014
New Revision: 212708

URL: http://llvm.org/viewvc/llvm-project?rev=212708&view=rev
Log:
Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."

This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/R600/select64.ll
    llvm/trunk/test/CodeGen/X86/shift-parts.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=212708&r1=212707&r2=212708&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul 10 06:37:28 2014
@@ -6022,20 +6022,6 @@ SDValue DAGCombiner::visitTRUNCATE(SDNod
     }
   }
 
-  // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
-  if (N0.getOpcode() == ISD::SELECT) {
-    EVT SrcVT = N0.getValueType();
-    if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
-        TLI.isTruncateFree(SrcVT, VT)) {
-      SDLoc SL(N0);
-      SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
-      SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
-      EVT SetCCVT = getSetCCResultType(VT);
-      SDValue Cond = DAG.getSExtOrTrunc(N0.getOperand(0), SL, SetCCVT);
-      return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
-    }
-  }
-
   // Fold a series of buildvector, bitcast, and truncate if possible.
   // For example fold
   //   (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to

Modified: llvm/trunk/test/CodeGen/R600/select64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/select64.ll?rev=212708&r1=212707&r2=212708&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/select64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/select64.ll Thu Jul 10 06:37:28 2014
@@ -13,38 +13,3 @@ entry:
   store i64 %1, i64 addrspace(1)* %out
   ret void
 }
-
-; CHECK-LABEL: @select_trunc_i64
-; CHECK: V_CNDMASK_B32
-; CHECK-NOT: V_CNDMASK_B32
-define void @select_trunc_i64(i32 addrspace(1)* %out, i32 %cond, i64 %in) nounwind {
-  %cmp = icmp ugt i32 %cond, 5
-  %sel = select i1 %cmp, i64 0, i64 %in
-  %trunc = trunc i64 %sel to i32
-  store i32 %trunc, i32 addrspace(1)* %out, align 4
-  ret void
-}
-
-; CHECK-LABEL: @select_trunc_i64_2
-; CHECK: V_CNDMASK_B32
-; CHECK-NOT: V_CNDMASK_B32
-define void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 %b) nounwind {
-  %cmp = icmp ugt i32 %cond, 5
-  %sel = select i1 %cmp, i64 %a, i64 %b
-  %trunc = trunc i64 %sel to i32
-  store i32 %trunc, i32 addrspace(1)* %out, align 4
-  ret void
-}
-
-; CHECK-LABEL: @v_select_trunc_i64_2
-; CHECK: V_CNDMASK_B32
-; CHECK-NOT: V_CNDMASK_B32
-define void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
-  %cmp = icmp ugt i32 %cond, 5
-  %a = load i64 addrspace(1)* %aptr, align 8
-  %b = load i64 addrspace(1)* %bptr, align 8
-  %sel = select i1 %cmp, i64 %a, i64 %b
-  %trunc = trunc i64 %sel to i32
-  store i32 %trunc, i32 addrspace(1)* %out, align 4
-  ret void
-}

Modified: llvm/trunk/test/CodeGen/X86/shift-parts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-parts.ll?rev=212708&r1=212707&r2=212708&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-parts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-parts.ll Thu Jul 10 06:37:28 2014
@@ -1,19 +1,17 @@
-; RUN: llc -march=x86-64 < %s | FileCheck %s
+; RUN: llc < %s -march=x86-64 | grep shrdq
 ; PR4736
 
 %0 = type { i32, i8, [35 x i8] }
 
 @g_144 = external global %0, align 8              ; <%0*> [#uses=1]
 
-; CHECK: shrdq
-
-define i32 @int87(i32 %uint64p_8, i1 %cond) nounwind {
+define i32 @int87(i32 %uint64p_8) nounwind {
 entry:
   %srcval4 = load i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
   br label %for.cond
 
 for.cond:                                         ; preds = %for.cond, %entry
-  %call3.in.in.in.v = select i1 %cond, i320 192, i320 128 ; <i320> [#uses=1]
+  %call3.in.in.in.v = select i1 undef, i320 192, i320 128 ; <i320> [#uses=1]
   %call3.in.in.in = lshr i320 %srcval4, %call3.in.in.in.v ; <i320> [#uses=1]
   %call3.in = trunc i320 %call3.in.in.in to i32   ; <i32> [#uses=1]
   %tobool = icmp eq i32 %call3.in, 0              ; <i1> [#uses=1]