[llvm] r212607 - [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions
Daniel Sanders
daniel.sanders at imgtec.com
Wed Jul 9 03:40:20 PDT 2014
Author: dsanders
Date: Wed Jul 9 05:40:20 2014
New Revision: 212607
URL: http://llvm.org/viewvc/llvm-project?rev=212607&view=rev
Log:
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions
Summary:
It seems we accidentally read the wrong column of the table MIPS64r6 spec
and used the names for c.cond.fmt instead of cmp.cond.fmt.
Differential Revision: http://reviews.llvm.org/D4387
Modified:
llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/test/CodeGen/Mips/analyzebranch.ll
llvm/trunk/test/CodeGen/Mips/fcmp.ll
llvm/trunk/test/CodeGen/Mips/select.ll
llvm/trunk/test/MC/Disassembler/Mips/mips32r6.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r6.txt
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td Wed Jul 9 05:40:20 2014
@@ -108,22 +108,23 @@ def FIELD_FMT_D : FIELD_FMT<0b10001>;
class FIELD_CMP_COND<bits<5> Val> {
bits<5> Value = Val;
}
-def FIELD_CMP_COND_F : FIELD_CMP_COND<0b00000>;
+// Note: The CMP_COND_FMT names differ from the C_COND_FMT names.
+def FIELD_CMP_COND_AF : FIELD_CMP_COND<0b00000>;
def FIELD_CMP_COND_UN : FIELD_CMP_COND<0b00001>;
def FIELD_CMP_COND_EQ : FIELD_CMP_COND<0b00010>;
def FIELD_CMP_COND_UEQ : FIELD_CMP_COND<0b00011>;
-def FIELD_CMP_COND_OLT : FIELD_CMP_COND<0b00100>;
+def FIELD_CMP_COND_LT : FIELD_CMP_COND<0b00100>;
def FIELD_CMP_COND_ULT : FIELD_CMP_COND<0b00101>;
-def FIELD_CMP_COND_OLE : FIELD_CMP_COND<0b00110>;
+def FIELD_CMP_COND_LE : FIELD_CMP_COND<0b00110>;
def FIELD_CMP_COND_ULE : FIELD_CMP_COND<0b00111>;
-def FIELD_CMP_COND_SF : FIELD_CMP_COND<0b01000>;
-def FIELD_CMP_COND_NGLE : FIELD_CMP_COND<0b01001>;
+def FIELD_CMP_COND_SAF : FIELD_CMP_COND<0b01000>;
+def FIELD_CMP_COND_SUN : FIELD_CMP_COND<0b01001>;
def FIELD_CMP_COND_SEQ : FIELD_CMP_COND<0b01010>;
-def FIELD_CMP_COND_NGL : FIELD_CMP_COND<0b01011>;
-def FIELD_CMP_COND_LT : FIELD_CMP_COND<0b01100>;
-def FIELD_CMP_COND_NGE : FIELD_CMP_COND<0b01101>;
-def FIELD_CMP_COND_LE : FIELD_CMP_COND<0b01110>;
-def FIELD_CMP_COND_NGT : FIELD_CMP_COND<0b01111>;
+def FIELD_CMP_COND_SUEQ : FIELD_CMP_COND<0b01011>;
+def FIELD_CMP_COND_SLT : FIELD_CMP_COND<0b01100>;
+def FIELD_CMP_COND_SULT : FIELD_CMP_COND<0b01101>;
+def FIELD_CMP_COND_SLE : FIELD_CMP_COND<0b01110>;
+def FIELD_CMP_COND_SULE : FIELD_CMP_COND<0b01111>;
class FIELD_CMP_FORMAT<bits<5> Val> {
bits<5> Value = Val;
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jul 9 05:40:20 2014
@@ -186,8 +186,8 @@ class CMP_CONDN_DESC_BASE<string CondStr
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
RegisterOperand FGROpnd>{
- def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
- CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
+ def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
ISA_MIPS32R6;
def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
@@ -198,42 +198,42 @@ multiclass CMP_CC_M <FIELD_CMP_FORMAT Fo
def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
ISA_MIPS32R6;
- def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
- CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
- ISA_MIPS32R6;
+ def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
+ ISA_MIPS32R6;
def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
ISA_MIPS32R6;
- def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
- CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
- ISA_MIPS32R6;
+ def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
+ ISA_MIPS32R6;
def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
ISA_MIPS32R6;
- def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
- CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
- ISA_MIPS32R6;
- def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
- CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
- ISA_MIPS32R6;
+ def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
+ ISA_MIPS32R6;
+ def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
+ ISA_MIPS32R6;
def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
ISA_MIPS32R6;
- def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
- CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
- ISA_MIPS32R6;
- def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
- ISA_MIPS32R6;
- def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
- CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
+ def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
+ ISA_MIPS32R6;
+ def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
ISA_MIPS32R6;
- def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
- ISA_MIPS32R6;
- def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
- CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
+ def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
+ ISA_MIPS32R6;
+ def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
ISA_MIPS32R6;
+ def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
+ ISA_MIPS32R6;
}
//===----------------------------------------------------------------------===//
@@ -754,9 +754,9 @@ def : MipsPat<(setgt f32:$lhs, f32:$rhs)
ISA_MIPS32R6;
def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
ISA_MIPS32R6;
-def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
+def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_LT_S f32:$lhs, f32:$rhs)>,
ISA_MIPS32R6;
-def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
+def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$lhs, f32:$rhs)>,
ISA_MIPS32R6;
def : MipsPat<(setne f32:$lhs, f32:$rhs),
(NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
@@ -774,9 +774,9 @@ def : MipsPat<(setgt f64:$lhs, f64:$rhs)
ISA_MIPS32R6;
def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
ISA_MIPS32R6;
-def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
+def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_LT_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
-def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
+def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
def : MipsPat<(setne f64:$lhs, f64:$rhs),
(NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
Modified: llvm/trunk/test/CodeGen/Mips/analyzebranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/analyzebranch.ll?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/analyzebranch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/analyzebranch.ll Wed Jul 9 05:40:20 2014
@@ -16,7 +16,7 @@ entry:
; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
-; GPR: cmp.olt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
+; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnez $[[GPRCC]], $BB
Modified: llvm/trunk/test/CodeGen/Mips/fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcmp.ll?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcmp.ll Wed Jul 9 05:40:20 2014
@@ -52,10 +52,10 @@ define i32 @ogt_f32(float %a, float %b)
; 64-C-DAG: c.ule.s $f12, $f13
; 64-C-DAG: movf $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f14, $f12
+; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f13, $f12
+; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp ogt float %a, %b
@@ -76,10 +76,10 @@ define i32 @oge_f32(float %a, float %b)
; 64-C-DAG: c.ult.s $f12, $f13
; 64-C-DAG: movf $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f14, $f12
+; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f13, $f12
+; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp oge float %a, %b
@@ -100,10 +100,10 @@ define i32 @olt_f32(float %a, float %b)
; 64-C-DAG: c.olt.s $f12, $f13
; 64-C-DAG: movt $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f12, $f14
+; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f12, $f13
+; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp olt float %a, %b
@@ -124,10 +124,10 @@ define i32 @ole_f32(float %a, float %b)
; 64-C-DAG: c.ole.s $f12, $f13
; 64-C-DAG: movt $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f12, $f14
+; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f12, $f13
+; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp ole float %a, %b
@@ -412,10 +412,10 @@ define i32 @ogt_f64(double %a, double %b
; 64-C-DAG: c.ule.d $f12, $f13
; 64-C-DAG: movf $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f14, $f12
+; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f13, $f12
+; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp ogt double %a, %b
@@ -436,10 +436,10 @@ define i32 @oge_f64(double %a, double %b
; 64-C-DAG: c.ult.d $f12, $f13
; 64-C-DAG: movf $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f14, $f12
+; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f13, $f12
+; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp oge double %a, %b
@@ -460,10 +460,10 @@ define i32 @olt_f64(double %a, double %b
; 64-C-DAG: c.olt.d $f12, $f13
; 64-C-DAG: movt $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f12, $f14
+; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f12, $f13
+; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp olt double %a, %b
@@ -484,10 +484,10 @@ define i32 @ole_f64(double %a, double %b
; 64-C-DAG: c.ole.d $f12, $f13
; 64-C-DAG: movt $[[T0]], $1, $fcc0
-; 32-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f12, $f14
+; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $2, $[[T0]]
-; 64-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f12, $f13
+; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $2, $[[T0]]
%1 = fcmp ole double %a, %b
Modified: llvm/trunk/test/CodeGen/Mips/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/select.ll Wed Jul 9 05:40:20 2014
@@ -252,7 +252,7 @@ entry:
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f0]], $[[F2]], $[[F3]]
+; 32R6: cmp.lt.s $[[CC:f0]], $[[F2]], $[[F3]]
; 32R6: sel.s $[[CC]], $f14, $f12
; 64: c.olt.s $f14, $f15
@@ -263,7 +263,7 @@ entry:
; 64R2: movt.s $f13, $f12, $fcc0
; 64R2: mov.s $f0, $f13
-; 64R6: cmp.olt.s $[[CC:f0]], $f14, $f15
+; 64R6: cmp.lt.s $[[CC:f0]], $f14, $f15
; 64R6: sel.s $[[CC]], $f13, $f12
%cmp = fcmp olt float %f2, %f3
@@ -289,7 +289,7 @@ entry:
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.s $[[CC]], $f14, $f12
; 64: c.ule.s $f14, $f15
@@ -300,7 +300,7 @@ entry:
; 64R2: movf.s $f13, $f12, $fcc0
; 64R2: mov.s $f0, $f13
-; 64R6: cmp.olt.s $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
; 64R6: sel.s $[[CC]], $f13, $f12
%cmp = fcmp ogt float %f2, %f3
@@ -326,7 +326,7 @@ entry:
; 32R6-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
; 32R6-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
-; 32R6: cmp.olt.s $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.d $[[CC]], $f14, $f12
; 64: c.ule.s $f14, $f15
@@ -337,7 +337,7 @@ entry:
; 64R2: movf.d $f13, $f12, $fcc0
; 64R2: mov.d $f0, $f13
-; 64R6: cmp.olt.s $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
; 64R6: sel.d $[[CC]], $f13, $f12
%cmp = fcmp ogt float %f2, %f3
@@ -400,7 +400,7 @@ entry:
; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.olt.d $[[CC:f0]], $[[F2]], $[[F3]]
+; 32R6: cmp.lt.d $[[CC:f0]], $[[F2]], $[[F3]]
; 32R6: sel.d $[[CC]], $f14, $f12
; 64: c.olt.d $f14, $f15
@@ -411,7 +411,7 @@ entry:
; 64R2: movt.d $f13, $f12, $fcc0
; 64R2: mov.d $f0, $f13
-; 64R6: cmp.olt.d $[[CC:f0]], $f14, $f15
+; 64R6: cmp.lt.d $[[CC:f0]], $f14, $f15
; 64R6: sel.d $[[CC]], $f13, $f12
%cmp = fcmp olt double %f2, %f3
@@ -437,7 +437,7 @@ entry:
; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.olt.d $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.d $[[CC]], $f14, $f12
; 64: c.ule.d $f14, $f15
@@ -448,7 +448,7 @@ entry:
; 64R2: movf.d $f13, $f12, $fcc0
; 64R2: mov.d $f0, $f13
-; 64R6: cmp.olt.d $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
; 64R6: sel.d $[[CC]], $f13, $f12
%cmp = fcmp ogt double %f2, %f3
@@ -477,7 +477,7 @@ entry:
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mthc1 $7, $[[F2]]
; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
-; 32R6: cmp.olt.d $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.s $[[CC]], $f14, $f12
; 64: c.ule.d $f14, $f15
@@ -488,7 +488,7 @@ entry:
; 64R2: movf.s $f13, $f12, $fcc0
; 64R2: mov.s $f0, $f13
-; 64R6: cmp.olt.d $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
; 64R6: sel.s $[[CC]], $f13, $f12
%cmp = fcmp ogt double %f2, %f3
@@ -561,7 +561,7 @@ entry:
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
+; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -577,7 +577,7 @@ entry:
; 64R2: movt $5, $4, $fcc0
; 64R2: move $2, $5
-; 64R6: cmp.olt.s $[[CC:f[0-9]+]], $f14, $f15
+; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -607,7 +607,7 @@ entry:
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -623,7 +623,7 @@ entry:
; 64R2: movf $5, $4, $fcc0
; 64R2: move $2, $5
-; 64R6: cmp.olt.s $[[CC:f[0-9]+]], $f15, $f14
+; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -745,7 +745,7 @@ entry:
; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
+; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -779,7 +779,7 @@ entry:
; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
+; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -824,7 +824,7 @@ entry:
; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
+; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
@@ -858,7 +858,7 @@ entry:
; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
+; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6.txt?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6.txt Wed Jul 9 05:40:20 2014
@@ -50,38 +50,38 @@
0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4
-0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4
+0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4
0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4
0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4
0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4
0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4
0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4
0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4
0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4
0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4
-0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4
+0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4
0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4
0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4
-0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4
-0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4
+0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
+0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4
0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r6.txt?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6.txt Wed Jul 9 05:40:20 2014
@@ -50,38 +50,38 @@
0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4
-0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4
+0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4
0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4
0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4
0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4
0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4
0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4
0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4
0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4
0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4
-0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4
+0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4
0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4
0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4
-0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4
-0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4
+0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
+0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4
0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4
-0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4
-0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
+0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4
+0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5
0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660
0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Wed Jul 9 05:40:20 2014
@@ -64,38 +64,38 @@
bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01]
bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25]
- cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
- cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
+ cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
+ cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81]
cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81]
cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82]
cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82]
cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83]
cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83]
- cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84]
- cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84]
+ cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84]
+ cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84]
cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85]
cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85]
- cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86]
- cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86]
+ cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86]
+ cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86]
cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87]
cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87]
- cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88]
- cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88]
- cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89]
- cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89]
+ cmp.saf.s $f2,$f3,$f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88]
+ cmp.saf.d $f2,$f3,$f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88]
+ cmp.sun.s $f2,$f3,$f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89]
+ cmp.sun.d $f2,$f3,$f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89]
cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a]
cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a]
- cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
- cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
- cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c]
- cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c]
- cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
- cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
- cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e]
- cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e]
- cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
- cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
+ cmp.sueq.s $f2,$f3,$f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
+ cmp.sueq.d $f2,$f3,$f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
+ cmp.slt.s $f2,$f3,$f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c]
+ cmp.slt.d $f2,$f3,$f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c]
+ cmp.sult.s $f2,$f3,$f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
+ cmp.sult.d $f2,$f3,$f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
+ cmp.sle.s $f2,$f3,$f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e]
+ cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e]
+ cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
+ cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=212607&r1=212606&r2=212607&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Wed Jul 9 05:40:20 2014
@@ -64,38 +64,38 @@
bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01]
bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25]
- cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
- cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
+ cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
+ cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81]
cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81]
cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82]
cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82]
cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83]
cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83]
- cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84]
- cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84]
+ cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84]
+ cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84]
cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85]
cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85]
- cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86]
- cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86]
+ cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86]
+ cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86]
cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87]
cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87]
- cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88]
- cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88]
- cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89]
- cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89]
+ cmp.saf.s $f2,$f3,$f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88]
+ cmp.saf.d $f2,$f3,$f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88]
+ cmp.sun.s $f2,$f3,$f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89]
+ cmp.sun.d $f2,$f3,$f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89]
cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a]
cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a]
- cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
- cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
- cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c]
- cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c]
- cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
- cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
- cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e]
- cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e]
- cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
- cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
+ cmp.sueq.s $f2,$f3,$f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
+ cmp.sueq.d $f2,$f3,$f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
+ cmp.slt.s $f2,$f3,$f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c]
+ cmp.slt.d $f2,$f3,$f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c]
+ cmp.sult.s $f2,$f3,$f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
+ cmp.sult.d $f2,$f3,$f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
+ cmp.sle.s $f2,$f3,$f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e]
+ cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e]
+ cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
+ cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
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