[PATCH] [AArch64]Fix an assertion failure about concating two build_vector in DAG Combiner

[Tim Northover]

Hi Hao,

I think you picked the right place to fix this. Even if you did patch AArch64, the bug would still be latent in the DAGCombiner.

I've just got one comment on the logic, really:

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10374-10376
@@ -10373,5 +10373,5 @@
 
-    for (unsigned i = 0; i != BuildVecNumElts; ++i)
-      Opnds.push_back(N0.getOperand(i));
-    for (unsigned i = 0; i != BuildVecNumElts; ++i)
-      Opnds.push_back(N1.getOperand(i));
+    EVT SclTy0 = N0.getOperand(0)->getValueType(0);
+    EVT SclTy1 = N1.getOperand(0)->getValueType(0);
+    if (SclTy0 == SclTy1) {
+      for (unsigned i = 0; i != BuildVecNumElts; ++i)
----------------
I think the logic here would be simpler if you defined an "EVT MinTy" and then truncated all inputs down to that in the loop. The trivial truncate operations will be automatically discarded in SelectionDAG::getNode.

http://reviews.llvm.org/D4417