[Mesa-dev] [PATCH 2/2] R600/SI: add sample and image intrinsics exposing all instruction fields
Marek Olšák
maraeo at gmail.com
Fri Jul 4 10:23:13 PDT 2014
Yeah, I can change that. I have never liked v*i8 types anyway.
However, the gather intrinsics already use v*i8. I will have to break
them if we want to use v*i32 everywhere.
Marek
On Fri, Jul 4, 2014 at 6:45 PM, Tom Stellard <tom at stellard.net> wrote:
> On Thu, Jul 03, 2014 at 06:26:05PM +0200, Marek Olšák wrote:
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> We need the intrinsics with offsets, so why not just add them all.
>> The R128 parameter will also be useful for reducing SGPR usage.
>> GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent",
>> so Mesa will probably translate those to slc, glc, etc.
>>
>> When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics.
>> ---
>> lib/Target/R600/SIInstructions.td | 159 +++++++++++----
>> lib/Target/R600/SIIntrinsics.td | 81 +++++++-
>> test/CodeGen/R600/llvm.SI.image.ll | 49 +++++
>> test/CodeGen/R600/llvm.SI.image.sample.ll | 289 ++++++++++++++++++++++++++++
>> test/CodeGen/R600/llvm.SI.image.sample.o.ll | 289 ++++++++++++++++++++++++++++
>> 5 files changed, 819 insertions(+), 48 deletions(-)
>> create mode 100644 test/CodeGen/R600/llvm.SI.image.ll
>> create mode 100644 test/CodeGen/R600/llvm.SI.image.sample.ll
>> create mode 100644 test/CodeGen/R600/llvm.SI.image.sample.o.ll
>>
>> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
>> index 291d634..25a9362 100644
>> --- a/lib/Target/R600/SIInstructions.td
>> +++ b/lib/Target/R600/SIInstructions.td
>> @@ -969,38 +969,38 @@ defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
>> //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
>> //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
>> //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
>> -defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
>> -//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
>> -defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
>> -//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
>> -defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
>> -defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
>> -//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
>> -//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
>> -defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
>> -//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
>> -defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
>> -//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
>> -defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
>> -defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
>> -//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
>> -//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
>> -//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
>> -//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
>> -//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
>> -//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
>> -//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
>> -//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
>> -//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
>> -//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
>> -//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
>> -//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
>> -//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
>> -//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
>> -//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
>> -//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
>> -//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
>> -//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
>> +defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
>> +defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">;
>> +defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
>> +defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">;
>> +defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
>> +defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
>> +defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">;
>> +defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">;
>> +defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
>> +defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">;
>> +defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
>> +defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">;
>> +defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
>> +defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
>> +defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">;
>> +defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">;
>> +defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">;
>> +defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">;
>> +defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">;
>> +defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">;
>> +defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">;
>> +defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">;
>> +defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">;
>> +defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">;
>> +defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">;
>> +defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">;
>> +defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">;
>> +defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">;
>> +defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">;
>> +defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">;
>> +defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">;
>> +defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">;
>> defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">;
>> defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">;
>> defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">;
>> @@ -1025,15 +1025,15 @@ defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">;
>> defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">;
>> defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">;
>> defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">;
>> -defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
>> -//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
>> -//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
>> -//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
>> -//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
>> -//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
>> -//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
>> -//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
>> -//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
>> +defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">;
>> +defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">;
>> +defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">;
>> +defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">;
>> +defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">;
>> +defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">;
>> +defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">;
>> +defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">;
>> +defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">;
>> //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
>> //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
>>
>> @@ -1849,6 +1849,7 @@ def : Pat <
>> /********** Image sampling patterns **********/
>> /********** ======================= **********/
>>
>> +// Image + sampler
>> class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
>> (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, i32:$dmask, i32:$unorm,
>> i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
>> @@ -1857,6 +1858,78 @@ class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat
>> $addr, $rsrc, $sampler)
>> >;
>>
>> +multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
>> + def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
>> + def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
>> + def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
>> + def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
>> + def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
>> +}
>> +
>> +// Image only
>> +class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
>> + (name vt:$addr, v32i8:$rsrc, i32:$dmask, i32:$unorm,
>> + i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
>> + (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
>> + (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
>> + $addr, $rsrc)
>> +>;
>> +
>> +multiclass ImagePatterns<SDPatternOperator name, string opcode> {
>> + def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
>> + def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
>> + def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
>> +}
>> +
>> +// Basic sample
>> +defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
>> +defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
>> +defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
>> +defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
>> +defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
>> +defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
>> +defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
>> +defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
>> +defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
>> +defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
>> +
>> +// Sample with comparison
>> +defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
>> +
>> +// Sample with offsets
>> +defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
>> +
>> +// Sample with comparison and offsets
>> +defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
>> +defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
>> +
>> +// Gather opcodes
>> // Only the variants which make sense are defined.
>> def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
>> def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
>> @@ -1901,6 +1974,10 @@ def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
>> def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
>> def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
>>
>> +def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
>> +defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
>> +defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
>> +
>> /* SIsample for simple 1D texture lookup */
>> def : Pat <
>> (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
>> diff --git a/lib/Target/R600/SIIntrinsics.td b/lib/Target/R600/SIIntrinsics.td
>> index df690a4..fc0c850 100644
>> --- a/lib/Target/R600/SIIntrinsics.td
>> +++ b/lib/Target/R600/SIIntrinsics.td
>> @@ -54,8 +54,6 @@ let TargetPrefix = "SI", isTarget = 1 in {
>>
>> def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
>>
>> - class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
>> -
>> // Fully-flexible SAMPLE instruction.
>> class SampleRaw : Intrinsic <
>> [llvm_v4f32_ty], // vdata(VGPR)
>> @@ -72,10 +70,68 @@ let TargetPrefix = "SI", isTarget = 1 in {
>> llvm_i32_ty], // lwe(imm)
>> [IntrNoMem]>;
>>
>> - def int_SI_sample : Sample;
>> - def int_SI_sampleb : Sample;
>> - def int_SI_sampled : Sample;
>> - def int_SI_samplel : Sample;
>> + // Image instruction without a sampler.
>> + class Image : Intrinsic <
>> + [llvm_v4f32_ty], // vdata(VGPR)
>> + [llvm_anyint_ty, // vaddr(VGPR)
>> + llvm_v32i8_ty, // rsrc(SGPR)
>
>
> We are trying to move away from using v*i8 types for resource descriptors,
> since it requires us to declare v32i8 as a legal type, which causes a lot
> of problems for us with the DAG Legalizer.
>
> We should use v8i32 here and also in SampleRaw we should use v8i32 for the
> resource and v4i32 for the sampler.
>
> -Tom
>
>
>> + llvm_i32_ty, // dmask(imm)
>> + llvm_i32_ty, // unorm(imm)
>> + llvm_i32_ty, // r128(imm)
>> + llvm_i32_ty, // da(imm)
>> + llvm_i32_ty, // glc(imm)
>> + llvm_i32_ty, // slc(imm)
>> + llvm_i32_ty, // tfe(imm)
>> + llvm_i32_ty], // lwe(imm)
>> + [IntrNoMem]>;
>> +
>> + // Basic sample
>> + def int_SI_image_sample : SampleRaw;
>> + def int_SI_image_sample_cl : SampleRaw;
>> + def int_SI_image_sample_d : SampleRaw;
>> + def int_SI_image_sample_d_cl : SampleRaw;
>> + def int_SI_image_sample_l : SampleRaw;
>> + def int_SI_image_sample_b : SampleRaw;
>> + def int_SI_image_sample_b_cl : SampleRaw;
>> + def int_SI_image_sample_lz : SampleRaw;
>> + def int_SI_image_sample_cd : SampleRaw;
>> + def int_SI_image_sample_cd_cl : SampleRaw;
>> +
>> + // Sample with comparison
>> + def int_SI_image_sample_c : SampleRaw;
>> + def int_SI_image_sample_c_cl : SampleRaw;
>> + def int_SI_image_sample_c_d : SampleRaw;
>> + def int_SI_image_sample_c_d_cl : SampleRaw;
>> + def int_SI_image_sample_c_l : SampleRaw;
>> + def int_SI_image_sample_c_b : SampleRaw;
>> + def int_SI_image_sample_c_b_cl : SampleRaw;
>> + def int_SI_image_sample_c_lz : SampleRaw;
>> + def int_SI_image_sample_c_cd : SampleRaw;
>> + def int_SI_image_sample_c_cd_cl : SampleRaw;
>> +
>> + // Sample with offsets
>> + def int_SI_image_sample_o : SampleRaw;
>> + def int_SI_image_sample_cl_o : SampleRaw;
>> + def int_SI_image_sample_d_o : SampleRaw;
>> + def int_SI_image_sample_d_cl_o : SampleRaw;
>> + def int_SI_image_sample_l_o : SampleRaw;
>> + def int_SI_image_sample_b_o : SampleRaw;
>> + def int_SI_image_sample_b_cl_o : SampleRaw;
>> + def int_SI_image_sample_lz_o : SampleRaw;
>> + def int_SI_image_sample_cd_o : SampleRaw;
>> + def int_SI_image_sample_cd_cl_o : SampleRaw;
>> +
>> + // Sample with comparison and offsets
>> + def int_SI_image_sample_c_o : SampleRaw;
>> + def int_SI_image_sample_c_cl_o : SampleRaw;
>> + def int_SI_image_sample_c_d_o : SampleRaw;
>> + def int_SI_image_sample_c_d_cl_o : SampleRaw;
>> + def int_SI_image_sample_c_l_o : SampleRaw;
>> + def int_SI_image_sample_c_b_o : SampleRaw;
>> + def int_SI_image_sample_c_b_cl_o : SampleRaw;
>> + def int_SI_image_sample_c_lz_o : SampleRaw;
>> + def int_SI_image_sample_c_cd_o : SampleRaw;
>> + def int_SI_image_sample_c_cd_cl_o : SampleRaw;
>>
>> // Basic gather4
>> def int_SI_gather4 : SampleRaw;
>> @@ -111,8 +167,19 @@ let TargetPrefix = "SI", isTarget = 1 in {
>>
>> def int_SI_getlod : SampleRaw;
>>
>> - def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
>> + // Image instrinsics.
>> + def int_SI_image_load : Image;
>> + def int_SI_image_load_mip : Image;
>> + def int_SI_getresinfo : Image;
>>
>> + // Deprecated image and sample intrinsics.
>> + class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
>> +
>> + def int_SI_sample : Sample;
>> + def int_SI_sampleb : Sample;
>> + def int_SI_sampled : Sample;
>> + def int_SI_samplel : Sample;
>> + def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
>> def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
>>
>> /* Interpolation Intrinsics */
>> diff --git a/test/CodeGen/R600/llvm.SI.image.ll b/test/CodeGen/R600/llvm.SI.image.ll
>> new file mode 100644
>> index 0000000..debe7c7
>> --- /dev/null
>> +++ b/test/CodeGen/R600/llvm.SI.image.ll
>> @@ -0,0 +1,49 @@
>> +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
>> +
>> +;CHECK-LABEL: @image_load
>> +;CHECK: IMAGE_LOAD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @image_load() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <32 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @image_load_mip
>> +;CHECK: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @image_load_mip() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32> undef, <32 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @getresinfo
>> +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @getresinfo() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.getresinfo.i32(i32 undef, <32 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +declare <4 x float> @llvm.SI.image.load.v4i32(<4 x i32>, <32 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32>, <32 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.getresinfo.i32(i32, <32 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +
>> +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>> +
>> +attributes #0 = { "ShaderType"="0" }
>> +attributes #1 = { nounwind readnone }
>> diff --git a/test/CodeGen/R600/llvm.SI.image.sample.ll b/test/CodeGen/R600/llvm.SI.image.sample.ll
>> new file mode 100644
>> index 0000000..20358b2
>> --- /dev/null
>> +++ b/test/CodeGen/R600/llvm.SI.image.sample.ll
>> @@ -0,0 +1,289 @@
>> +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
>> +
>> +;CHECK-LABEL: @sample
>> +;CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_cl
>> +;CHECK: IMAGE_SAMPLE_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_d
>> +;CHECK: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_d() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_d_cl
>> +;CHECK: IMAGE_SAMPLE_D_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_d_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_l
>> +;CHECK: IMAGE_SAMPLE_L {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_l() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_b
>> +;CHECK: IMAGE_SAMPLE_B {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_b() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_b_cl
>> +;CHECK: IMAGE_SAMPLE_B_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_b_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_lz
>> +;CHECK: IMAGE_SAMPLE_LZ {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_lz() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_cd
>> +;CHECK: IMAGE_SAMPLE_CD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_cd() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_cd_cl
>> +;CHECK: IMAGE_SAMPLE_CD_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_cd_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c
>> +;CHECK: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_cl
>> +;CHECK: IMAGE_SAMPLE_C_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_d
>> +;CHECK: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_d() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_d_cl
>> +;CHECK: IMAGE_SAMPLE_C_D_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_d_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_l
>> +;CHECK: IMAGE_SAMPLE_C_L {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_l() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_b
>> +;CHECK: IMAGE_SAMPLE_C_B {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_b() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_b_cl
>> +;CHECK: IMAGE_SAMPLE_C_B_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_b_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_lz
>> +;CHECK: IMAGE_SAMPLE_C_LZ {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_lz() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_cd
>> +;CHECK: IMAGE_SAMPLE_C_CD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_cd() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_cd_cl
>> +;CHECK: IMAGE_SAMPLE_C_CD_CL {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_cd_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +
>> +declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +
>> +declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +
>> +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>> +
>> +attributes #0 = { "ShaderType"="0" }
>> +attributes #1 = { nounwind readnone }
>> diff --git a/test/CodeGen/R600/llvm.SI.image.sample.o.ll b/test/CodeGen/R600/llvm.SI.image.sample.o.ll
>> new file mode 100644
>> index 0000000..6a79466
>> --- /dev/null
>> +++ b/test/CodeGen/R600/llvm.SI.image.sample.o.ll
>> @@ -0,0 +1,289 @@
>> +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
>> +
>> +;CHECK-LABEL: @sample
>> +;CHECK: IMAGE_SAMPLE_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_cl
>> +;CHECK: IMAGE_SAMPLE_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_d
>> +;CHECK: IMAGE_SAMPLE_D_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_d() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_d_cl
>> +;CHECK: IMAGE_SAMPLE_D_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_d_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_l
>> +;CHECK: IMAGE_SAMPLE_L_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_l() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_b
>> +;CHECK: IMAGE_SAMPLE_B_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_b() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_b_cl
>> +;CHECK: IMAGE_SAMPLE_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_b_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_lz
>> +;CHECK: IMAGE_SAMPLE_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_lz() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_cd
>> +;CHECK: IMAGE_SAMPLE_CD_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_cd() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_cd_cl
>> +;CHECK: IMAGE_SAMPLE_CD_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_cd_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c
>> +;CHECK: IMAGE_SAMPLE_C_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_cl
>> +;CHECK: IMAGE_SAMPLE_C_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_d
>> +;CHECK: IMAGE_SAMPLE_C_D_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_d() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_d_cl
>> +;CHECK: IMAGE_SAMPLE_C_D_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_d_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_l
>> +;CHECK: IMAGE_SAMPLE_C_L_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_l() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_b
>> +;CHECK: IMAGE_SAMPLE_C_B_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_b() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_b_cl
>> +;CHECK: IMAGE_SAMPLE_C_B_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_b_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_lz
>> +;CHECK: IMAGE_SAMPLE_C_LZ_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_lz() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_cd
>> +;CHECK: IMAGE_SAMPLE_C_CD_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_cd() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +;CHECK-LABEL: @sample_c_cd_cl
>> +;CHECK: IMAGE_SAMPLE_C_CD_CL_O {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
>> +define void @sample_c_cd_cl() #0 {
>> +main_body:
>> + %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>> + %r0 = extractelement <4 x float> %r, i32 0
>> + %r1 = extractelement <4 x float> %r, i32 1
>> + %r2 = extractelement <4 x float> %r, i32 2
>> + %r3 = extractelement <4 x float> %r, i32 3
>> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3)
>> + ret void
>> +}
>> +
>> +
>> +declare <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +
>> +declare <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +declare <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>> +
>> +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>> +
>> +attributes #0 = { "ShaderType"="0" }
>> +attributes #1 = { nounwind readnone }
>> --
>> 1.9.1
>>
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