[PATCH] [AArch64] Fix a build_vector pattern fail caused by defect in isBuildVectorAllZeros().

[Kevin Qin]

Ping...


2014-07-01 17:05 GMT+08:00 Kevin Qin <kevinqindev at gmail.com>:

> Sorry for following up this issue late. This patch is to normalize all
> constants building a vector. The value of constant nodes will be truncated
> to fit element width.
>
> http://reviews.llvm.org/D4228
>
> Files:
>   lib/Target/AArch64/AArch64ISelLowering.cpp
>   test/CodeGen/AArch64/arm64-build-vector.ll
>
> Index: lib/Target/AArch64/AArch64ISelLowering.cpp
> ===================================================================
> --- lib/Target/AArch64/AArch64ISelLowering.cpp
> +++ lib/Target/AArch64/AArch64ISelLowering.cpp
> @@ -5181,11 +5181,37 @@
>    return Op;
>  }
>
> +// Normalize the operands of BUILD_VECTOR. The value of constant operands
> will
> +// be truncated to fit element width.
> +static SDValue NormalizeBuildVector(SDValue Op,
> +                                    SelectionDAG &DAG) {
> +  assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
> +  SDLoc dl(Op);
> +  EVT VT = Op.getValueType();
> +  EVT EltTy= VT.getVectorElementType();
> +
> +  if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
> +    return Op;
> +
> +  SmallVector<SDValue, 16> Ops;
> +  for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
> +    SDValue Lane = Op.getOperand(I);
> +    if (Lane.getOpcode() == ISD::Constant) {
> +      APInt LowBits(EltTy.getSizeInBits(),
> +                    cast<ConstantSDNode>(Lane)->getZExtValue());
> +      Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
> +    }
> +    Ops.push_back(Lane);
> +  }
> +  return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
> +}
> +
>  SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
>                                                   SelectionDAG &DAG) const
> {
> -  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
>    SDLoc dl(Op);
>    EVT VT = Op.getValueType();
> +  Op = NormalizeBuildVector(Op, DAG);
> +  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
>
>    APInt CnstBits(VT.getSizeInBits(), 0);
>    APInt UndefBits(VT.getSizeInBits(), 0);
> Index: test/CodeGen/AArch64/arm64-build-vector.ll
> ===================================================================
> --- test/CodeGen/AArch64/arm64-build-vector.ll
> +++ test/CodeGen/AArch64/arm64-build-vector.ll
> @@ -36,7 +36,7 @@
>
>  define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
>  ; CHECK-LABEL: build_all_zero:
> -; CHECK: movn  w[[GREG:[0-9]+]], #0x517f
> +; CHECK: movz  w[[GREG:[0-9]+]], #0xae80
>  ; CHECK-NEXT:  fmov    s[[FREG:[0-9]+]], w[[GREG]]
>  ; CHECK-NEXT:  mul.8h  v0, v0, v[[FREG]]
>    %b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef,
> i16 undef, i16 undef, i16 undef, i16 undef>
>



-- 
Best Regards,

Kevin Qin
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