[PATCH] [AArch64] Enhance rematerialization by adding a new API isAsCheapAsAMove in TargetInstroInfo

[Quentin Colombet]

Hi Jiangning,

Thanks for the updated version.

Inline a few comments.

Cheers,
-Quentin

================
Comment at: include/llvm/Target/TargetInstrInfo.h:206
@@ +205,3 @@
+  ///
+  /// Targets for different archs need to override this, and different u-archs
+  /// can also be finely tuned inside.
----------------
Like Eric said:
u-archs => microarchitectures

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:1615
@@ -1614,3 +1614,3 @@
                   SDPatternOperator OpNode = null_frag> {
-  let hasSideEffects = 0 in {
+  let hasSideEffects = 0, isReMaterializable = 1 in {
   // Add/Subtract immediate
----------------
Since we are overriding the behavior of isAsCheapAsMove, I think it would make sense to set the isAsCheapAsMove flag as well as the isRematerializable flag.

What do you think?

Also, we may want to check the uses of isAsCheapAsMove to see if we should "promote" them to the new target hook.

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:1681
@@ -1680,3 +1680,3 @@
 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
-  let isCompare = 1, Defs = [NZCV] in {
+  let isCompare = 1, Defs = [NZCV], isReMaterializable = 1 in {
   // Add/Subtract immediate
----------------
I believe this is a remaining of the rematerialization of the  S variants. This should be removed. 

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:1954
@@ -1953,3 +1953,3 @@
 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
-  let isCompare = 1, Defs = [NZCV] in {
+  let isCompare = 1, Defs = [NZCV], isReMaterializable = 1 in {
   def Wri  : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
----------------
Same here: Shouldn't be rematerializable.

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:2001
@@ -1999,1 +2000,3 @@
+  let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0,
+      isReMaterializable = 1 in {
   def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
----------------
Ditto.

================
Comment at: lib/Target/AArch64/AArch64InstrInfo.cpp:558
@@ +557,3 @@
+      if (MI->getOperand(3).getImm() != 0)
+        return false;
+      else
----------------
Simply: return MI->getOperand(3).getImm() == 0

http://reviews.llvm.org/D4361