[PATCH] SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors

[Tom Stellard]

Ping.

On Thu, Jun 12, 2014 at 09:52:37AM -0700, Tom Stellard wrote:
> This patch adds isAllOnes and isAllZeros helpers for SDNodes that
> checks both ConstantSDNodes and BuildVectorSDNodes.
> ---
>  include/llvm/CodeGen/SelectionDAGNodes.h  |  9 +++++++++
>  lib/CodeGen/SelectionDAG/DAGCombiner.cpp  |  8 ++++----
>  lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 10 ++++++++++
>  test/CodeGen/R600/setcc-equivalent.ll     |  1 -
>  4 files changed, 23 insertions(+), 5 deletions(-)
> 
> diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
> index b209268..4dd0bda 100644
> --- a/include/llvm/CodeGen/SelectionDAGNodes.h
> +++ b/include/llvm/CodeGen/SelectionDAGNodes.h
> @@ -94,6 +94,15 @@ namespace ISD {
>    /// all ConstantSDNode or undef.
>    bool isBuildVectorOfConstantSDNodes(const SDNode *N);
>  
> +  /// \brief Return true if \p N is a constant with all bits set or a
> +  //  BUILD_VECTOR of all ~0 values.
> +  bool isAllOnes(const SDNode *N);
> +
> +  /// \brief Return true if \p N is a constant no bits set or a
> +  //  BUILD_VECTOR of all 0 values.
> +  bool isAllZeros(const SDNode *N);
> +
> +
>    /// isScalarToVector - Return true if the specified node is a
>    /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
>    /// element is not an undef.
> diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> index 0f50184..2ec3271 100644
> --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> @@ -2758,24 +2758,24 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
>      ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
>      ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
>  
> -    if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
> +    if (LR == RR && Op0 == Op1 &&
>          LL.getValueType().isInteger()) {
>        // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
> -      if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
> +      if (ISD::isAllZeros(LR.getNode()) && Op1 == ISD::SETEQ) {
>          SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
>                                       LR.getValueType(), LL, RL);
>          AddToWorkList(ORNode.getNode());
>          return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
>        }
>        // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
> -      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
> +      if (ISD::isAllOnes(LR.getNode()) && Op1 == ISD::SETEQ) {
>          SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
>                                        LR.getValueType(), LL, RL);
>          AddToWorkList(ANDNode.getNode());
>          return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
>        }
>        // fold (and (setgt X,  -1), (setgt Y,  -1)) -> (setgt (or X, Y), -1)
> -      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
> +      if (ISD::isAllOnes(LR.getNode()) && Op1 == ISD::SETGT) {
>          SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
>                                       LR.getValueType(), LL, RL);
>          AddToWorkList(ORNode.getNode());
> diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> index 010431e..e015e83 100644
> --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> @@ -232,6 +232,16 @@ bool ISD::allOperandsUndef(const SDNode *N) {
>    return true;
>  }
>  
> +bool ISD::isAllOnes(const SDNode *N) {
> +  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
> +  return (CN && CN->isAllOnesValue()) || ISD::isBuildVectorAllOnes(N);
> +}
> +
> +bool ISD::isAllZeros(const SDNode *N) {
> +  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
> +  return (CN && CN->isNullValue()) || ISD::isBuildVectorAllZeros(N);
> +}
> +
>  ISD::NodeType ISD::getExtForLoadExtType(ISD::LoadExtType ExtType) {
>    switch (ExtType) {
>    case ISD::EXTLOAD:
> diff --git a/test/CodeGen/R600/setcc-equivalent.ll b/test/CodeGen/R600/setcc-equivalent.ll
> index f796748..4c50aa3 100644
> --- a/test/CodeGen/R600/setcc-equivalent.ll
> +++ b/test/CodeGen/R600/setcc-equivalent.ll
> @@ -1,5 +1,4 @@
>  ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
> -; XFAIL: *
>  
>  ; EG-LABEL: @and_setcc_setcc_i32
>  ; EG: AND_INT
> -- 
> 1.8.1.4
> 
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