[PATCH] [x86] Begin a significant overhaul of how vector lowering is done in the x86 backend.

[Filipe Cabecinhas]

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:7005
@@ +7004,3 @@
+  //
+  // [0, 1, 2, 7, 4, 5, 6, 3] -PSHUFD[0,2,1,3]-> [0, 1, 4, 7, 2, 3, 6, 5]
+  //
----------------
This seems wrong. How can you have [{0,1}{2,7}{4,5}{6,3}] -> [{0,1}{4,7}{2,3}{6,5}]? How did the {2,7} get mixed with the {4,5}? Wouldn't pshufd just shuffle double words around but not break them?

Shouldn't it become [{0,1}{4,5}{2,7}{6,3}]?

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Comment at: lib/Target/X86/X86ISelLowering.cpp:7013
@@ +7012,3 @@
+                  std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
+                 2;
+    int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
----------------
Commenting how that subtraction gets us the index that's not used would be nice.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:7073
@@ +7072,3 @@
+    // a dword.
+    int AdjIndex = (InPlaceInputs[0] & ~1) + ((InPlaceInputs[0] + 1) % 2);
+    SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
----------------
Wouldn't InPlaceInputs[0] ^ 1 do the same thing? And it would be the same trick you used in the previous function.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:7401
@@ +7400,3 @@
+  if (NumV1Inputs + NumV2Inputs <= 4)
+    return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
+
----------------
NumV1Inputs == 0 && NumV2Inputs == 4 => assert in lowerV8I16BasicBlendVectorShuffle:7293

The previous if should have an else if (NumV1Inputs == 0) ...SingleInput...(...V2...)

If this condition doesn't arise because it's been handled earlier, I'd like to have an assert here.

http://reviews.llvm.org/D4225