[llvm] r211679 - [X86] Add target combine rule to select ADDSUB instructions from a build_vector

[Andrea Di Biagio]

Hi Hal,

I can confirm that after r211427 we correctly match a 'subadd' into a
x86 ADDSUB instruction.
To verify this I redirected to ' llc -mcpu=core-i7-avx' the output of
test 'addsub.ll' added at revision r211339.

So,

opt < addsub.ll -basicaa -slp-vectorizer -S | llc -march=x86-64
-mcpu=corei7-avx | less

you can see how we correctly emit an 'addsub' instruction in the case
of function @fsubfadd.
We don't emit an 'addsub' for the other functions but that's fine for
the following reasons:
 1- 'addsub' on X86 is only for packed float vectors (therefore - we
cannot match an 'addsub' in case of functions @addsub and @subadd);
 2- the semantic of 'addsub' for x86 requires that even-numbered
elements are subtracted (not added). That means, we cannot match an
'addsub' in function @faddfsub.

Instead, we correctly match an 'addsub' in the case of function @fsubfadd.

On x86, excluding function @fsubfadd, other functions cannot be
translated using 'addsubps/addsubpd' (and their AVX variants).

I hope this helps :-)

Andrea

On Wed, Jun 25, 2014 at 12:01 PM, Andrea Di Biagio
<andrea.dibiagio at gmail.com> wrote:
> Hi Hal,
>
>
>
> On Wed, Jun 25, 2014 at 11:35 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>> Does this mean that we now match the form of these produced by the SLP vectorizer? (see r211339)
>>
>>  -Hal
>>
>
> Interesting, apparently I missed that commit...
> I'll have a look at it now.
>
> -Andrea