[llvm] r211565 - [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields

[Adam Nemet]

Author: anemet
Date: Mon Jun 23 20:42:32 2014
New Revision: 211565

URL: http://llvm.org/viewvc/llvm-project?rev=211565&view=rev
Log:
[Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields

V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields.  This was simply not used in the decoder until now.

Fixes <rdar://problem/17402661>

Modified:
    llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
    llvm/trunk/test/MC/Disassembler/X86/avx-512.txt

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=211565&r1=211564&r2=211565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Mon Jun 23 20:42:32 2014
@@ -1620,7 +1620,8 @@ static int readVVVV(struct InternalInstr
 
   int vvvv;
   if (insn->vectorExtensionType == TYPE_EVEX)
-    vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
+    vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
+            vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]));
   else if (insn->vectorExtensionType == TYPE_VEX_3B)
     vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
   else if (insn->vectorExtensionType == TYPE_VEX_2B)

Modified: llvm/trunk/test/MC/Disassembler/X86/avx-512.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/avx-512.txt?rev=211565&r1=211564&r2=211565&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/avx-512.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/avx-512.txt Mon Jun 23 20:42:32 2014
@@ -39,6 +39,12 @@
 # CHECK: vgatherdpd      (%rsi,%ymm0,4), %zmm1 {%k2}
 0x62 0xf2 0xfd 0x4a 0x92 0x0c 0x86
 
+# CHECK: vpslld $16, %zmm21, %zmm22
+0x62 0xb1 0x4d 0x40 0x72 0xf5 0x10
+
+# CHECK: vpord %zmm22, %zmm21, %zmm23
+0x62 0xa1 0x55 0x40 0xeb 0xfe
+
 #####################################################
 #                MASK INSTRUCTIONS                  #
 #####################################################