Invalid base register with fast-isel

[Hal Finkel]

----- Original Message -----
> From: "Ulrich Weigand" <Ulrich.Weigand at de.ibm.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "llvm-commits" <llvm-commits at cs.uiuc.edu>
> Sent: Monday, June 23, 2014 7:57:22 AM
> Subject: Invalid base register with fast-isel
> 
> 
> 
> Hi Hal,
> 
> I've run into a bug where current LLVM at -O0 (with fast-isel)
> generated
> invalid code like:
> 
>         ld 0, 20936(1)                  # 8-byte Folded Reload
>         stw 12, 10348(0)
>         stw 12, 10344(0)
> 
> This happens (at the moment -- register allocation problems tend to
> be
> fragile) with the following .ll code:
> (See attached file: nullbaseregbug.ll)
> 
> For some reason, the underlying vreg was allocated as G8RC instead of
> G8RC_NOX0.   That vreg came originally from
> PPCRegisterInfo::materializeFrameBaseRegister.  Changing the register
> class
> there (along the lines of the attached patch) seems to fix the
> problem for
> me, but I'm not really sure whether this is right solution.   How is
> register class selection supposed to work with fast-isel?   Isn't the
> presence of the vreg inside an address supposed to be enough to
> ensure use
> of the G8RC_NOX0 class?

Yes, it is. But I suspect that the FastISel code that is creating those STW instructions is not correctly setting (or constraining) the register class for the base address operand. Maybe a call to constrainRegClass is needed in PPCFastISel::PPCComputeAddress near where the Instruction::Alloca case is handled?

Thanks again,
Hal

> (See attached file: diff-llvm-fix-fastiselreg)
> 
> 
> Mit freundlichen Gruessen / Best Regards
> 
> Ulrich Weigand
> 
> --
>   Dr. Ulrich Weigand | Phone: +49-7031/16-3727
>   STSM, GNU/Linux compilers and toolchain
>   IBM Deutschland Research & Development GmbH
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-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory