[PATCH] R600/SI: Add verifier check for immediates in register operands.

[Matt Arsenault]

On Jun 20, 2014, at 9:39 AM, Tom Stellard <thomas.stellard at amd.com> wrote:

> ---
> lib/Target/R600/SIInstrInfo.cpp    |  9 ++++++++-
> lib/Target/R600/SIInstructions.td  |  2 +-
> lib/Target/R600/SIRegisterInfo.cpp | 16 ++++++++++++++++
> lib/Target/R600/SIRegisterInfo.h   |  8 ++++++++
> 4 files changed, 33 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
> index f5b82d5..70350d6 100644
> --- a/lib/Target/R600/SIInstrInfo.cpp
> +++ b/lib/Target/R600/SIInstrInfo.cpp
> @@ -542,7 +542,14 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
>   // Make sure the register classes are correct
>   for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
>     switch (Desc.OpInfo[i].OperandType) {
> -    case MCOI::OPERAND_REGISTER:
> +    case MCOI::OPERAND_REGISTER: {
> +      int RegClass = Desc.OpInfo[i].RegClass;
> +      if (!RI.regClassCanUseImmediate(RegClass) &&
> +          (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
> +        ErrInfo = "Expected register, but got immediate";
> +        return false;
> +      }
> +    }
>       break;
>     case MCOI::OPERAND_IMMEDIATE:
>       if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 26024dc..a2eff4b 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1626,7 +1626,7 @@ let usesCustomInserter = 1 in {
> // constant that can be used with the ADDR64 MUBUF instructions.
> def SI_ADDR64_RSRC : InstSI <
>   (outs SReg_128:$srsrc),
> -  (ins SReg_64:$ptr),
> +  (ins SSrc_64:$ptr),
>   "", []
>> ;
> 
> diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp
> index 519a7ba..d0b677a 100644
> --- a/lib/Target/R600/SIRegisterInfo.cpp
> +++ b/lib/Target/R600/SIRegisterInfo.cpp
> @@ -125,3 +125,19 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
>   unsigned Index = getHWRegIndex(Reg);
>   return SubRC->getRegister(Index + Channel);
> }
> +
> +bool SIRegisterInfo::regClassCanUseImmediate(int RCID) const {
> +  switch (RCID) {
> +  default: return false;
> +  case AMDGPU::SSrc_32RegClassID:
> +  case AMDGPU::SSrc_64RegClassID:
> +  case AMDGPU::VSrc_32RegClassID:
> +  case AMDGPU::VSrc_64RegClassID:
> +    return true;
> +  }
> +}
> +
> +bool SIRegisterInfo::regClassCanUseImmediate(
> +                             const TargetRegisterClass *RC) const {
> +  return regClassCanUseImmediate(RC->getID());
> +}
> diff --git a/lib/Target/R600/SIRegisterInfo.h b/lib/Target/R600/SIRegisterInfo.h
> index 6bcf2f0..c9305fb 100644
> --- a/lib/Target/R600/SIRegisterInfo.h
> +++ b/lib/Target/R600/SIRegisterInfo.h
> @@ -60,6 +60,14 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
>   /// \returns The sub-register of Reg that is in Channel.
>   unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
>                             unsigned Channel) const;
> +
> +  /// \returns True if operands defined with this register class can accept
> +  /// inline immediates.
> +  bool regClassCanUseImmediate(int RCID) const;
> +
> +  /// \returns True if operands defined with this register class can accept
> +  /// inline immediates.
> +  bool regClassCanUseImmediate(const TargetRegisterClass *RC) const;
> };
> 
> } // End namespace llvm
> -- 
> 1.8.1.5

LGTM