[llvm] r211254 - Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
Alp Toker
alp at nuanti.com
Thu Jun 19 00:03:52 PDT 2014
On 19/06/2014 09:10, Craig Topper wrote:
> Author: ctopper
> Date: Thu Jun 19 01:10:58 2014
> New Revision: 211254
>
> URL: http://llvm.org/viewvc/llvm-project?rev=211254&view=rev
> Log:
> Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
Hi Craig,
While working on this commit did you get a feel for whether we could get
rid of the llvm_unreachable() string parameter?
The llvm_unreachable("Unexpected enum value/XYZ") messages always looked
less-than-useful to me. Unlike asserts they get used in places that are
genuinely unreachable, even used as an optimisation hint in release
builds. As a result the strings are seldom seen, making the small but
conscious effort it takes to write them somewhat demeaning.
Alp.
>
> Modified:
> llvm/trunk/include/llvm/Support/StreamableMemoryObject.h
> llvm/trunk/lib/MC/ELFObjectWriter.cpp
> llvm/trunk/lib/TableGen/Record.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
> llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
> llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
> llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Support/StreamableMemoryObject.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StreamableMemoryObject.h?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/StreamableMemoryObject.h (original)
> +++ llvm/trunk/include/llvm/Support/StreamableMemoryObject.h Thu Jun 19 01:10:58 2014
> @@ -13,6 +13,7 @@
>
> #include "llvm/Support/Compiler.h"
> #include "llvm/Support/DataStream.h"
> +#include "llvm/Support/ErrorHandling.h"
> #include "llvm/Support/MemoryObject.h"
> #include <cassert>
> #include <memory>
> @@ -115,7 +116,7 @@ public:
> // requiring that the bitcode size be known, or otherwise ensuring that
> // the memory doesn't go away/get reallocated, but it's
> // not currently necessary. Users that need the pointer don't stream.
> - assert(0 && "getPointer in streaming memory objects not allowed");
> + llvm_unreachable("getPointer in streaming memory objects not allowed");
> return nullptr;
> }
> bool isValidAddress(uint64_t address) const override;
> @@ -154,8 +155,8 @@ private:
> kChunkSize);
> BytesRead += bytes;
> if (bytes < kChunkSize) {
> - if (ObjectSize && BytesRead < Pos)
> - assert(0 && "Unexpected short read fetching bitcode");
> + assert((!ObjectSize || BytesRead >= Pos) &&
> + "Unexpected short read fetching bitcode");
> if (BytesRead <= Pos) { // reached EOF/ran out of bytes
> ObjectSize = BytesRead;
> EOFReached = true;
>
> Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
> +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Jun 19 01:10:58 2014
> @@ -1574,8 +1574,7 @@ void ELFObjectWriter::WriteSection(MCAss
> break;
>
> default:
> - assert(0 && "FIXME: sh_type value not supported!");
> - break;
> + llvm_unreachable("FIXME: sh_type value not supported!");
> }
>
> if (TargetObjectWriter->getEMachine() == ELF::EM_ARM &&
>
> Modified: llvm/trunk/lib/TableGen/Record.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/Record.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/TableGen/Record.cpp (original)
> +++ llvm/trunk/lib/TableGen/Record.cpp Thu Jun 19 01:10:58 2014
> @@ -811,20 +811,14 @@ Init *UnOpInit::Fold(Record *CurRec, Mul
> }
> case HEAD: {
> if (ListInit *LHSl = dyn_cast<ListInit>(LHS)) {
> - if (LHSl->getSize() == 0) {
> - assert(0 && "Empty list in car");
> - return nullptr;
> - }
> + assert(LHSl->getSize() != 0 && "Empty list in car");
> return LHSl->getElement(0);
> }
> break;
> }
> case TAIL: {
> if (ListInit *LHSl = dyn_cast<ListInit>(LHS)) {
> - if (LHSl->getSize() == 0) {
> - assert(0 && "Empty list in cdr");
> - return nullptr;
> - }
> + assert(LHSl->getSize() != 0 && "Empty list in cdr");
> // Note the +1. We can't just pass the result of getValues()
> // directly.
> ArrayRef<Init *>::iterator begin = LHSl->getValues().begin()+1;
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Jun 19 01:10:58 2014
> @@ -823,8 +823,7 @@ AArch64TargetLowering::EmitInstrWithCust
> #ifndef NDEBUG
> MI->dump();
> #endif
> - assert(0 && "Unexpected instruction for custom inserter!");
> - break;
> + llvm_unreachable("Unexpected instruction for custom inserter!");
>
> case AArch64::F128CSEL:
> return EmitF128CSEL(MI, BB);
> @@ -833,7 +832,6 @@ AArch64TargetLowering::EmitInstrWithCust
> case TargetOpcode::PATCHPOINT:
> return emitPatchPoint(MI, BB);
> }
> - llvm_unreachable("Unexpected instruction for custom inserter!");
> }
>
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Thu Jun 19 01:10:58 2014
> @@ -3447,8 +3447,7 @@ bool AArch64AsmParser::showMatchError(SM
> case Match_MnemonicFail:
> return Error(Loc, "unrecognized instruction mnemonic");
> default:
> - assert(0 && "unexpected error code!");
> - return Error(Loc, "invalid instruction format");
> + llvm_unreachable("unexpected error code!");
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp Thu Jun 19 01:10:58 2014
> @@ -37,8 +37,7 @@ getVariant(uint64_t LLVMDisassembler_Var
> case LLVMDisassembler_VariantKind_ARM64_TLVP:
> case LLVMDisassembler_VariantKind_ARM64_TLVOFF:
> default:
> - assert(0 && "bad LLVMDisassembler_VariantKind");
> - return MCSymbolRefExpr::VK_None;
> + llvm_unreachable("bad LLVMDisassembler_VariantKind");
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp Thu Jun 19 01:10:58 2014
> @@ -218,13 +218,9 @@ AArch64MCCodeEmitter::getMachineOpValue(
> const MCSubtargetInfo &STI) const {
> if (MO.isReg())
> return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
> - else {
> - assert(MO.isImm() && "did not expect relocated expression");
> - return static_cast<unsigned>(MO.getImm());
> - }
>
> - assert(0 && "Unable to encode MCOperand!");
> - return 0;
> + assert(MO.isImm() && "did not expect relocated expression");
> + return static_cast<unsigned>(MO.getImm());
> }
>
> template<unsigned FixupKind> uint32_t
>
> Modified: llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp Thu Jun 19 01:10:58 2014
> @@ -321,8 +321,7 @@ unsigned A15SDOptimizer::optimizeSDPatte
> return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
> }
>
> - assert(0 && "Unhandled update pattern!");
> - return 0;
> + llvm_unreachable("Unhandled update pattern!");
> }
>
> // Return true if this MachineInstr inserts a scalar (SPR) value into
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Thu Jun 19 01:10:58 2014
> @@ -1047,8 +1047,7 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(co
> // we have a movt or a movw, but that led to misleadingly results.
> // This is now disallowed in the the AsmParser in validateInstruction()
> // so this should never happen.
> - assert(0 && "expression without :upper16: or :lower16:");
> - return 0;
> + llvm_unreachable("expression without :upper16: or :lower16:");
> }
>
> uint32_t ARMMCCodeEmitter::
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu Jun 19 01:10:58 2014
> @@ -1538,14 +1538,13 @@ int HexagonInstrInfo::GetDotOldOp(const
> int NewOp = opc;
> if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
> NewOp = Hexagon::getPredOldOpcode(NewOp);
> - if (NewOp < 0)
> - assert(0 && "Couldn't change predicate new instruction to its old form.");
> + assert(NewOp >= 0 &&
> + "Couldn't change predicate new instruction to its old form.");
> }
>
> if (isNewValueStore(NewOp)) { // Convert into non-new-value format
> NewOp = Hexagon::getNonNVStore(NewOp);
> - if (NewOp < 0)
> - assert(0 && "Couldn't change new-value store to its old form.");
> + assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
> }
> return NewOp;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Thu Jun 19 01:10:58 2014
> @@ -65,7 +65,7 @@ public:
> const MCRelaxableFragment *DF,
> const MCAsmLayout &Layout) const override {
> // FIXME.
> - assert(0 && "RelaxInstruction() unimplemented");
> + llvm_unreachable("RelaxInstruction() unimplemented");
> return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp Thu Jun 19 01:10:58 2014
> @@ -172,17 +172,13 @@ uint64_t R600MCCodeEmitter::getMachineOp
> SmallVectorImpl<MCFixup> &Fixup,
> const MCSubtargetInfo &STI) const {
> if (MO.isReg()) {
> - if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
> + if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
> return MRI.getEncodingValue(MO.getReg());
> - } else {
> - return getHWReg(MO.getReg());
> - }
> - } else if (MO.isImm()) {
> - return MO.getImm();
> - } else {
> - assert(0);
> - return 0;
> + return getHWReg(MO.getReg());
> }
> +
> + assert(MO.isImm());
> + return MO.getImm();
> }
>
> #include "AMDGPUGenMCCodeEmitter.inc"
>
> Modified: llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp Thu Jun 19 01:10:58 2014
> @@ -173,6 +173,6 @@ void SparcInstPrinter::printCCOperand(co
> bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
> raw_ostream &O)
> {
> - assert(0 && "FIXME: Implement SparcInstPrinter::printGetPCX.");
> + llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
> return true;
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Thu Jun 19 01:10:58 2014
> @@ -196,7 +196,7 @@ namespace {
> const MCRelaxableFragment *DF,
> const MCAsmLayout &Layout) const override {
> // FIXME.
> - assert(0 && "fixupNeedsRelaxation() unimplemented");
> + llvm_unreachable("fixupNeedsRelaxation() unimplemented");
> return false;
> }
> void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
>
> Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp?rev=211254&r1=211253&r2=211254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp Thu Jun 19 01:10:58 2014
> @@ -133,7 +133,7 @@ getMachineOpValue(const MCInst &MI, cons
> if (Expr->EvaluateAsAbsolute(Res))
> return Res;
>
> - assert(0 && "Unhandled expression!");
> + llvm_unreachable("Unhandled expression!");
> return 0;
> }
>
>
>
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