[PATCH 1/1] R600: Implement zero undef variants of ctlz/cttz

[Matt Arsenault]

On 06/18/2014 07:26 AM, Jan Vesely wrote:
> Hi Matt,
>
> this is the rebased version. It's nicer than the original series,
> and it does not include 64 bit version.
> There's one thing that confuses me though. The generated code for vector
> ops looks like this:
>            FFBL_INT              * T1.W, T0.W,
>            FFBL_INT              * T1.Z, T0.Z,
>            FFBL_INT              * T1.Y, T0.Y,
>            FFBL_INT                T1.X, T0.X,
>            LSHR                  * T0.X, KC0[2].Y, literal.x,
>
> The manual says that FFBX family are vector unit only instruction, so shouldn't
> there be more than 1 per instruction group?
>
> regards,
> Jan
I don't know much about the details of R600's ISA. By vector unit, I 
would assume it means the 4 XYZW components as opposed to the 5th 
transcendental slot, so this would be correct.