[PATCH] Add support to recognize non SIMD kind of parallelism in SLPVectorizer

[hfinkel at anl.gov]

Thanks for working on this!

================
Comment at: lib/Transforms/Vectorize/SLPVectorizer.cpp:178
@@ +177,3 @@
+    if (!I || Opcode != I->getOpcode()) {
+      if (Opcode == Instruction::FAdd && i == 1)
+        return isAddSubInst(VL);
----------------
Can we add support for matching (fsub, fadd, fsub, fadd, ...)? I think that generating (fneg ( addsub (x, y))) would be nice.

Also, is there any particular reason that we're restricting this to floating-point add/sub? Granted, I know of no ISA with integer add/sub instructions, but I think that the lowering as (addsub ( x, xor (y, mask))) is likely more efficient than the scalar version.

================
Comment at: test/Transforms/SLPVectorizer/X86/addsub.ll:13
@@ +12,3 @@
+; CHECK: fsub <4 x float>
+; CHECK: shufflevector
+; Function Attrs: nounwind uwtable
----------------
Please check the actual shuffle indices

================
Comment at: test/Transforms/SLPVectorizer/X86/addsub.ll:39
@@ +38,3 @@
+
+!0 = metadata !{metadata !"clang version 3.5.0 (209794)"}
+!1 = metadata !{metadata !2, metadata !2, i64 0}
----------------
We don't need this ident metadata in the test files.

http://reviews.llvm.org/D4015