[PATCH] Add a SubTargetFeature to enable Post RA Scheduling

[Sanjay Patel]

Hi nadav,

Currently, there's an "X86ProcFamily" enum that is used to enable post-register-allocator code scheduling for Atom CPU variants. 

This patch is the first step in removing that enum by creating a new SubTargetFeature for PostRA Scheduling that can be used by any CPU. This will clean up the code and make it easier to debug potential postRA scheduler problems (see PR20020).

No change to codegen for any target is intended with this patch.

Patch author: Simon Pilgrim

http://reviews.llvm.org/D4183

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86Subtarget.cpp
  lib/Target/X86/X86Subtarget.h

Index: lib/Target/X86/X86.td
===================================================================
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -170,6 +170,9 @@
                                    "LEA instruction with certain arguments is slow">;
 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
                                    "INC and DEC instructions are slower than ADD and SUB">;
+def FeaturePostRAScheduler : SubtargetFeature<"sched-post-ra",
+                                   "PostRAScheduler", "true",
+                                   "Enable post register allocation scheduling">;

 //===----------------------------------------------------------------------===//
 // X86 processors supported.
@@ -221,7 +224,7 @@
                       FeatureSlowDivide,
                       FeatureCallRegIndirect,
                       FeatureLEAUsesAG,
-                      FeaturePadShortFunctions]>;
+                      FeaturePadShortFunctions, FeaturePostRAScheduler]>;

 // Atom Silvermont.
 def : ProcessorModel<"slm",  SLMModel, [ProcIntelSLM,
@@ -231,7 +234,8 @@
                                FeatureCallRegIndirect,
                                FeaturePRFCHW,
                                FeatureSlowLEA, FeatureSlowIncDec,
-                               FeatureSlowBTMem, FeatureFastUAMem]>;
+                               FeatureSlowBTMem, FeatureFastUAMem,
+                               FeaturePostRAScheduler]>;
 // "Arrandale" along with corei3 and corei5
 def : ProcessorModel<"corei7", SandyBridgeModel,
                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
Index: lib/Target/X86/X86Subtarget.cpp
===================================================================
--- lib/Target/X86/X86Subtarget.cpp
+++ lib/Target/X86/X86Subtarget.cpp
@@ -219,9 +219,6 @@
   // Make sure the right MCSchedModel is used.
   InitCPUSchedModel(CPUName);

-  if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
-    PostRAScheduler = true;
-
   InstrItins = getInstrItineraryForCPU(CPUName);

   // It's important to keep the MCSubtargetInfo feature bits in sync with
Index: lib/Target/X86/X86Subtarget.h
===================================================================
--- lib/Target/X86/X86Subtarget.h
+++ lib/Target/X86/X86Subtarget.h
@@ -453,7 +453,7 @@
   /// Enable the MachineScheduler pass for all X86 subtargets.
   bool enableMachineScheduler() const override { return true; }

-  /// enablePostRAScheduler - run for Atom optimization.
+  /// enablePostRAScheduler - set by FeaturePostRAScheduler subtargetfeature.
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                              TargetSubtargetInfo::AntiDepBreakMode& Mode,
                              RegClassVector& CriticalPathRCs) const override;
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