[PATCH 1/3] R600: Implement 64bit SHL
Tom Stellard
tom at stellard.net
Tue Jun 17 14:08:15 PDT 2014
On Tue, Jun 17, 2014 at 04:50:03PM -0400, Jan Vesely wrote:
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
> lib/Target/R600/R600ISelLowering.cpp | 42 +++++++++++++
> lib/Target/R600/R600ISelLowering.h | 1 +
> test/CodeGen/R600/shl.ll | 117 ++++++++++++++++++++++++++++++++++-
> 3 files changed, 158 insertions(+), 2 deletions(-)
>
> diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> index beea54e..33dc1b3 100644
> --- a/lib/Target/R600/R600ISelLowering.cpp
> +++ b/lib/Target/R600/R600ISelLowering.cpp
> @@ -157,6 +157,10 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
> setOperationAction(ISD::UDIV, MVT::i64, Custom);
> setOperationAction(ISD::UREM, MVT::i64, Custom);
>
> + // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
> + // to be Legal/Custom in order to avoid library calls.
> + setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
> +
> setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
>
> setBooleanContents(ZeroOrNegativeOneBooleanContent);
> @@ -552,6 +556,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
> default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
> case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
> case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
> + case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
> case ISD::FCOS:
> case ISD::FSIN: return LowerTrig(Op, DAG);
> case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
> @@ -905,6 +910,43 @@ SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
> DAG.getConstantFP(3.14159265359, MVT::f32));
> }
>
> +SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
> + SDLoc DL(Op);
> + EVT VT = Op.getValueType();
> +
> + SDValue Lo = Op.getOperand(0);
> + SDValue Hi = Op.getOperand(1);
> + SDValue Shift = Op.getOperand(2);
> + SDValue Zero = DAG.getConstant(0, VT);
> + SDValue One = DAG.getConstant(1, VT);
> +
> + SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
> + SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
> + SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
> + SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
> +
> + /* The dance around Width1 is necessary for 0 special case.
> + * Without it the CompShift might be 32, producing incorrect results in
> + * Overflow. So we do the shift in two steps, the alternative is to
> + * add a conditional to filter the special case.
> + */
> +
Use c++ style comments here: //
Otherwise, LGTM.
> + SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
> + Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
> +
> + SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
> + HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
> + SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
> +
> + SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
> + SDValue LoBig = Zero;
> +
> + Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
> + Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
> +
> + return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
> +}
> +
> SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
> return DAG.getNode(
> ISD::SETCC,
> diff --git a/lib/Target/R600/R600ISelLowering.h b/lib/Target/R600/R600ISelLowering.h
> index ed12dab..a7d8374 100644
> --- a/lib/Target/R600/R600ISelLowering.h
> +++ b/lib/Target/R600/R600ISelLowering.h
> @@ -60,6 +60,7 @@ private:
> SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
> + SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
>
> SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
> SelectionDAG &DAG) const;
> diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll
> index 4a6aab4..43fab2a 100644
> --- a/test/CodeGen/R600/shl.ll
> +++ b/test/CodeGen/R600/shl.ll
> @@ -39,5 +39,118 @@ define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in
> ret void
> }
>
> -; XXX: Add SI test for i64 shl once i64 stores and i64 function arguments are
> -; supported.
> +;EG-CHECK: @shl_i64
> +;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
> +;EG-CHECK: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
> +;EG-CHECK: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
> +;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
> +;EG-CHECK-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]]
> +;EG-CHECK-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
> +;EG-CHECK-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]}}
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
> +;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
> +;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
> +
> +;SI-CHECK: @shl_i64
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +
> +define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
> + %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
> + %a = load i64 addrspace(1) * %in
> + %b = load i64 addrspace(1) * %b_ptr
> + %result = shl i64 %a, %b
> + store i64 %result, i64 addrspace(1)* %out
> + ret void
> +}
> +
> +;EG-CHECK: @shl_v2i64
> +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
> +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
> +;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHA]]
> +;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHB]]
> +;EG-CHECK-DAG: LSHR {{.*}}, 1
> +;EG-CHECK-DAG: LSHR {{.*}}, 1
> +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
> +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]]
> +;EG-CHECK-DAG: LSHL
> +;EG-CHECK-DAG: LSHL
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
> +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> +;EG-CHECK-DAG: CNDE_INT
> +;EG-CHECK-DAG: CNDE_INT
> +
> +;SI-CHECK: @shl_v2i64
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +
> +define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
> + %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
> + %a = load <2 x i64> addrspace(1) * %in
> + %b = load <2 x i64> addrspace(1) * %b_ptr
> + %result = shl <2 x i64> %a, %b
> + store <2 x i64> %result, <2 x i64> addrspace(1)* %out
> + ret void
> +}
> +
> +;EG-CHECK: @shl_v4i64
> +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
> +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
> +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
> +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
> +;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHA]]
> +;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHB]]
> +;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHC]]
> +;EG-CHECK-DAG: LSHR {{\*? *}}[[COMPSHD]]
> +;EG-CHECK-DAG: LSHR {{.*}}, 1
> +;EG-CHECK-DAG: LSHR {{.*}}, 1
> +;EG-CHECK-DAG: LSHR {{.*}}, 1
> +;EG-CHECK-DAG: LSHR {{.*}}, 1
> +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
> +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
> +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
> +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHC]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHD]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHA]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHB]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHC]]
> +;EG-CHECK-DAG: LSHL {{.*}}, [[SHD]]
> +;EG-CHECK-DAG: LSHL
> +;EG-CHECK-DAG: LSHL
> +;EG-CHECK-DAG: LSHL
> +;EG-CHECK-DAG: LSHL
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
> +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
> +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> +;EG-CHECK-DAG: CNDE_INT
> +;EG-CHECK-DAG: CNDE_INT
> +;EG-CHECK-DAG: CNDE_INT
> +;EG-CHECK-DAG: CNDE_INT
> +
> +;SI-CHECK: @shl_v4i64
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +;SI-CHECK: V_LSHL_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> +
> +define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
> + %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
> + %a = load <4 x i64> addrspace(1) * %in
> + %b = load <4 x i64> addrspace(1) * %b_ptr
> + %result = shl <4 x i64> %a, %b
> + store <4 x i64> %result, <4 x i64> addrspace(1)* %out
> + ret void
> +}
> --
> 1.9.3
>
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