[PATCH] forbid 8-byte atomic on Cortex M

[Phoebe Buckheister]

On Mon, 16 Jun 2014 18:29:45 +0100, Tim Northover wrote:
> H Phoebe
> 
> On 16 June 2014 18:18, Phoebe Buckheister <llvm at quasiparticle.net>
> wrote:
> > Cortex M profiles don't support atomic operations on double words at
> > all, but LLVM will happily codegen them anyway. Smaller atomics are
> > available just fine on M profiles, so just disable atomics on
> > anything larger than a machine word.
> 
> Don't think the behaviour for loads and stores is quite right. The
> only reason we expand 64-bit ones on the usual ARM architectures is
> that ldrd and strd aren't guaranteed to be atomic. On Cortex-M it
> seems there simply are no 64-bit atomic operations, but that doesn't
> mean a 32-bit load suddenly becomes non-atomic.
> 
> So I'd suggest leaving the first two conditions as they are (64-bit
> operations won't work either way, but you'll get better code for
> 32-bit ones).

Thanks for the feedback. Initially I had left those first two
conditions alone, but then llvm will generate ldrexd/strexd
instructions in the testcase I also added. I don't think that's quite
right either, so I might be missing something I should've changed
elsewhere.

I did miss the smaller loads/stores though, so maybe the first
two conditions should be <= AtomicLimit instead?

> Cheers.
> 
> Tim.