[PATCH] ARMEB: Fix trunc store for vector types

[Christian Pirker]

I committed this patch as rL211010.

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Comment at: test/CodeGen/ARM/big-endian-neon-trunc-store.ll:17
@@ +16,3 @@
+; CHECK-LABEL: vector_trunc_store_4i32_to_4i8:
+; CHECK:       vmovn.i32 [[REG:d[0-9]+]]
+; CHECK:       vrev16.8  [[REG]], [[REG]]
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James Molloy wrote:
> I just tried your patch, and this test case is producing another REV just above this line. Is that expected? If so, please add it as a CHECK line so that it is obvioiusly expected behaviour.
The vrev64.32 instruction that you are observing, belongs to a bundle of vld and vrev to load a vector from memory. This instruction sequence for load is not touched by this patch and therefore a CHECK line for the vrev instruction is purposely not included.

http://reviews.llvm.org/D4135