[llvm] r210916 - Atomics: switch direction of cmpxchg comparison
Tim Northover
tnorthover at apple.com
Fri Jun 13 09:45:36 PDT 2014
Author: tnorthover
Date: Fri Jun 13 11:45:36 2014
New Revision: 210916
URL: http://llvm.org/viewvc/llvm-project?rev=210916&view=rev
Log:
Atomics: switch direction of cmpxchg comparison
This has two benefits: it makes the result more suitable for direct
insertaion into the struct to emulate the new cmpxchg, and it means
the name we give the instruction matches its actual effect better.
Modified:
llvm/trunk/lib/CodeGen/AtomicExpandLoadLinkedPass.cpp
llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll
llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll
Modified: llvm/trunk/lib/CodeGen/AtomicExpandLoadLinkedPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AtomicExpandLoadLinkedPass.cpp?rev=210916&r1=210915&r2=210916&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AtomicExpandLoadLinkedPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/AtomicExpandLoadLinkedPass.cpp Fri Jun 13 11:45:36 2014
@@ -283,9 +283,9 @@ bool AtomicExpandLoadLinked::expandAtomi
Builder.SetInsertPoint(TryStoreBB);
Value *StoreSuccess = TLI->emitStoreConditional(
Builder, CI->getNewValOperand(), Addr, MemOpOrder);
- Value *TryAgain = Builder.CreateICmpNE(
+ StoreSuccess = Builder.CreateICmpEQ(
StoreSuccess, ConstantInt::get(Type::getInt32Ty(Ctx), 0), "success");
- Builder.CreateCondBr(TryAgain, LoopBB, BarrierBB);
+ Builder.CreateCondBr(StoreSuccess, BarrierBB, LoopBB);
// Make sure later instructions don't get reordered with a fence if necessary.
Builder.SetInsertPoint(BarrierBB);
Modified: llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll?rev=210916&r1=210915&r2=210916&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll (original)
+++ llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll Fri Jun 13 11:45:36 2014
@@ -234,8 +234,8 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst
; CHECK: [[TRY_STORE]]:
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[TRY_STORE]] ], [ false, %[[LOOP]] ]
@@ -264,8 +264,8 @@ define i16 @test_cmpxchg_i16_seqcst_mono
; CHECK: [[TRY_STORE]]:
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK: fence seq_cst
@@ -292,8 +292,8 @@ define i32 @test_cmpxchg_i32_acquire_acq
; CHECK: [[TRY_STORE]]:
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr)
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[TRY_STORE]] ], [ false, %[[LOOP]] ]
@@ -331,8 +331,8 @@ define i64 @test_cmpxchg_i64_monotonic_m
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK-NOT: fence
Modified: llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll?rev=210916&r1=210915&r2=210916&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll (original)
+++ llvm/trunk/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll Fri Jun 13 11:45:36 2014
@@ -96,8 +96,8 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst
; CHECK: [[TRY_STORE]]:
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[TRY_STORE]] ], [ false, %[[LOOP]] ]
@@ -126,8 +126,8 @@ define i16 @test_cmpxchg_i16_seqcst_mono
; CHECK: [[TRY_STORE]]:
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK-NOT: fence
@@ -154,8 +154,8 @@ define i32 @test_cmpxchg_i32_acquire_acq
; CHECK: [[TRY_STORE]]:
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr)
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[TRY_STORE]] ], [ false, %[[LOOP]] ]
@@ -193,8 +193,8 @@ define i64 @test_cmpxchg_i64_monotonic_m
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
-; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
-; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[BARRIER:.*]]
+; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
+; CHECK: br i1 [[TST]], label %[[BARRIER:.*]], label %[[LOOP]]
; CHECK: [[BARRIER]]:
; CHECK-NOT: fence
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