[PATCH] R600: Mostly remove remaining AMDIL intrinsics.
Tom Stellard
tom at stellard.net
Thu Jun 12 14:09:11 PDT 2014
On Thu, Jun 12, 2014 at 07:25:01PM +0000, Matt Arsenault wrote:
> Delete all unused ones, and add new AMDGPU named intrinsics for
> the ones that are. Handle the old AMDIL names for comptability (although
> remove their GCCBuiltin names) and add tests since there weren't any
> for these before.
>
LGTM.
> http://reviews.llvm.org/D4126
>
> Files:
> lib/Target/R600/AMDGPUISelLowering.cpp
> lib/Target/R600/AMDGPUISelLowering.h
> lib/Target/R600/AMDGPUInstrInfo.td
> lib/Target/R600/AMDGPUInstructions.td
> lib/Target/R600/AMDGPUIntrinsics.td
> lib/Target/R600/AMDILInstrInfo.td
> lib/Target/R600/AMDILIntrinsics.td
> lib/Target/R600/SIInstructions.td
> test/CodeGen/R600/llvm.rint.ll
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -743,26 +743,26 @@
>
> switch (IntrinsicID) {
> default: return Op;
> - case AMDGPUIntrinsic::AMDIL_abs:
> + case AMDGPUIntrinsic::AMDGPU_abs:
> + case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
> return LowerIntrinsicIABS(Op, DAG);
> - case AMDGPUIntrinsic::AMDIL_exp:
> - return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
> case AMDGPUIntrinsic::AMDGPU_lrp:
> return LowerIntrinsicLRP(Op, DAG);
> - case AMDGPUIntrinsic::AMDIL_fraction:
> + case AMDGPUIntrinsic::AMDGPU_fract:
> + case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
> return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
> - case AMDGPUIntrinsic::AMDIL_max:
> - return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
> - Op.getOperand(2));
> +
> + case AMDGPUIntrinsic::AMDGPU_clamp:
> + case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
> + return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
> + Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
> +
> case AMDGPUIntrinsic::AMDGPU_imax:
> return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
> Op.getOperand(2));
> case AMDGPUIntrinsic::AMDGPU_umax:
> return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
> Op.getOperand(2));
> - case AMDGPUIntrinsic::AMDIL_min:
> - return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
> - Op.getOperand(2));
> case AMDGPUIntrinsic::AMDGPU_imin:
> return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
> Op.getOperand(2));
> @@ -821,7 +821,10 @@
> Op.getOperand(1),
> Op.getOperand(2));
>
> - case AMDGPUIntrinsic::AMDIL_round_nearest:
> + case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
> + return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
> +
> + case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
> return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
> }
> }
> @@ -1567,6 +1570,7 @@
> // AMDGPU DAG nodes
> NODE_NAME_CASE(DWORDADDR)
> NODE_NAME_CASE(FRACT)
> + NODE_NAME_CASE(CLAMP)
> NODE_NAME_CASE(FMAX)
> NODE_NAME_CASE(SMAX)
> NODE_NAME_CASE(UMAX)
> Index: lib/Target/R600/AMDGPUISelLowering.h
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.h
> +++ lib/Target/R600/AMDGPUISelLowering.h
> @@ -177,6 +177,7 @@
> // End AMDIL ISD Opcodes
> DWORDADDR,
> FRACT,
> + CLAMP,
> COS_HW,
> SIN_HW,
> FMAX,
> Index: lib/Target/R600/AMDGPUInstrInfo.td
> ===================================================================
> --- lib/Target/R600/AMDGPUInstrInfo.td
> +++ lib/Target/R600/AMDGPUInstrInfo.td
> @@ -34,6 +34,8 @@
> [SDNPCommutative, SDNPAssociative]
> >;
>
> +def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
> +
> // out = max(a, b) a and b are signed ints
> def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
> [SDNPCommutative, SDNPAssociative]
> Index: lib/Target/R600/AMDGPUInstructions.td
> ===================================================================
> --- lib/Target/R600/AMDGPUInstructions.td
> +++ lib/Target/R600/AMDGPUInstructions.td
> @@ -302,7 +302,7 @@
> (outs rc:$dst),
> (ins rc:$src0),
> "CLAMP $dst, $src0",
> - [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
> + [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
> >;
>
> class FABS <RegisterClass rc> : AMDGPUShaderInst <
> Index: lib/Target/R600/AMDGPUIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDGPUIntrinsics.td
> +++ lib/Target/R600/AMDGPUIntrinsics.td
> @@ -18,10 +18,12 @@
> def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
> def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
> -
> + def int_AMDGPU_abs : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
> def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
> def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
> def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
> + def int_AMDGPU_fract : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> + def int_AMDGPU_clamp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
> def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
> def int_AMDGPU_kilp : Intrinsic<[], [], []>;
> @@ -65,6 +67,15 @@
> def int_AMDGPU_barrier_local : Intrinsic<[], [], []>;
> }
>
> +// Legacy names for compatability.
> +let TargetPrefix = "AMDIL", isTarget = 1 in {
> + def int_AMDIL_abs : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> + def int_AMDIL_fraction : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> + def int_AMDIL_clamp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> + def int_AMDIL_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> + def int_AMDIL_round_nearest : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> +}
> +
> let TargetPrefix = "TGSI", isTarget = 1 in {
>
> def int_TGSI_lit_z : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],[IntrNoMem]>;
> Index: lib/Target/R600/AMDILInstrInfo.td
> ===================================================================
> --- lib/Target/R600/AMDILInstrInfo.td
> +++ lib/Target/R600/AMDILInstrInfo.td
> @@ -143,8 +143,3 @@
> def _f32 : ILFormat<(outs), (ins GPRF32:$src0, GPRF32:$src1),
> !strconcat(name, " $src0, $src1"), []>;
> }
> -
> -//===--------------------------------------------------------------------===//
> -// Intrinsics support
> -//===--------------------------------------------------------------------===//
> -include "AMDILIntrinsics.td"
> Index: lib/Target/R600/AMDILIntrinsics.td
> ===================================================================
> --- lib/Target/R600/AMDILIntrinsics.td
> +++ /dev/null
> @@ -1,221 +0,0 @@
> -//===- AMDILIntrinsics.td - Defines AMDIL Intrinscs -*- tablegen -*-===//
> -//
> -// The LLVM Compiler Infrastructure
> -//
> -// This file is distributed under the University of Illinois Open Source
> -// License. See LICENSE.TXT for details.
> -//
> -//==-----------------------------------------------------------------------===//
> -//
> -// This file defines all of the amdil-specific intrinsics
> -//
> -//===---------------------------------------------------------------===//
> -//===--------------------------------------------------------------------===//
> -// Intrinsic classes
> -// Generic versions of the above classes but for Target specific intrinsics
> -// instead of SDNode patterns.
> -//===--------------------------------------------------------------------===//
> -let TargetPrefix = "AMDIL", isTarget = 1 in {
> - class VoidIntLong :
> - Intrinsic<[llvm_i64_ty], [], []>;
> - class VoidIntInt :
> - Intrinsic<[llvm_i32_ty], [], []>;
> - class VoidIntBool :
> - Intrinsic<[llvm_i32_ty], [], []>;
> - class UnaryIntInt :
> - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> - class UnaryIntFloat :
> - Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
> - class ConvertIntFTOI :
> - Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
> - class ConvertIntITOF :
> - Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], [IntrNoMem]>;
> - class UnaryIntNoRetInt :
> - Intrinsic<[], [llvm_anyint_ty], []>;
> - class UnaryIntNoRetFloat :
> - Intrinsic<[], [llvm_anyfloat_ty], []>;
> - class BinaryIntInt :
> - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> - class BinaryIntFloat :
> - Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> - class BinaryIntNoRetInt :
> - Intrinsic<[], [llvm_anyint_ty, LLVMMatchType<0>], []>;
> - class BinaryIntNoRetFloat :
> - Intrinsic<[], [llvm_anyfloat_ty, LLVMMatchType<0>], []>;
> - class TernaryIntInt :
> - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
> - LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> - class TernaryIntFloat :
> - Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>,
> - LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> - class QuaternaryIntInt :
> - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
> - LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
> - class UnaryAtomicInt :
> - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
> - class BinaryAtomicInt :
> - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
> - class TernaryAtomicInt :
> - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>;
> - class UnaryAtomicIntNoRet :
> - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
> - class BinaryAtomicIntNoRet :
> - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
> - class TernaryAtomicIntNoRet :
> - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
> -}
> -
> -let TargetPrefix = "AMDIL", isTarget = 1 in {
> - def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
> - def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
> - UnaryIntInt;
> - def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">,
> - UnaryIntInt;
> - def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">,
> - UnaryIntInt;
> - def int_AMDIL_bit_find_first_sgn : GCCBuiltin<"__amdil_ffb_signed">,
> - UnaryIntInt;
> - def int_AMDIL_media_bitalign : GCCBuiltin<"__amdil_bitalign">,
> - TernaryIntInt;
> - def int_AMDIL_media_bytealign : GCCBuiltin<"__amdil_bytealign">,
> - TernaryIntInt;
> - def int_AMDIL_bit_insert_u32 : GCCBuiltin<"__amdil_ubit_insert">,
> - QuaternaryIntInt;
> - def int_AMDIL_bfi : GCCBuiltin<"__amdil_bfi">,
> - TernaryIntInt;
> - def int_AMDIL_bfm : GCCBuiltin<"__amdil_bfm">,
> - BinaryIntInt;
> - def int_AMDIL_mulhi_i32 : GCCBuiltin<"__amdil_imul_high">,
> - BinaryIntInt;
> - def int_AMDIL_mulhi_u32 : GCCBuiltin<"__amdil_umul_high">,
> - BinaryIntInt;
> - def int_AMDIL_mulhi24_i32 : GCCBuiltin<"__amdil_imul24_high">,
> - BinaryIntInt;
> - def int_AMDIL_mulhi24_u32 : GCCBuiltin<"__amdil_umul24_high">,
> - BinaryIntInt;
> - def int_AMDIL_carry_i32 : GCCBuiltin<"__amdil_carry">,
> - BinaryIntInt;
> - def int_AMDIL_borrow_i32 : GCCBuiltin<"__amdil_borrow">,
> - BinaryIntInt;
> - def int_AMDIL_min_i32 : GCCBuiltin<"__amdil_imin">,
> - BinaryIntInt;
> - def int_AMDIL_min_u32 : GCCBuiltin<"__amdil_umin">,
> - BinaryIntInt;
> - def int_AMDIL_min : GCCBuiltin<"__amdil_min">,
> - BinaryIntFloat;
> - def int_AMDIL_max_i32 : GCCBuiltin<"__amdil_imax">,
> - BinaryIntInt;
> - def int_AMDIL_max_u32 : GCCBuiltin<"__amdil_umax">,
> - BinaryIntInt;
> - def int_AMDIL_max : GCCBuiltin<"__amdil_max">,
> - BinaryIntFloat;
> - def int_AMDIL_media_lerp_u4 : GCCBuiltin<"__amdil_u4lerp">,
> - TernaryIntInt;
> - def int_AMDIL_media_sad : GCCBuiltin<"__amdil_sad">,
> - TernaryIntInt;
> - def int_AMDIL_media_sad_hi : GCCBuiltin<"__amdil_sadhi">,
> - TernaryIntInt;
> - def int_AMDIL_fraction : GCCBuiltin<"__amdil_fraction">,
> - UnaryIntFloat;
> - def int_AMDIL_clamp : GCCBuiltin<"__amdil_clamp">,
> - TernaryIntFloat;
> - def int_AMDIL_pireduce : GCCBuiltin<"__amdil_pireduce">,
> - UnaryIntFloat;
> - def int_AMDIL_round_nearest : GCCBuiltin<"__amdil_round_nearest">,
> - UnaryIntFloat;
> - def int_AMDIL_round_neginf : GCCBuiltin<"__amdil_round_neginf">,
> - UnaryIntFloat;
> - def int_AMDIL_round_zero : GCCBuiltin<"__amdil_round_zero">,
> - UnaryIntFloat;
> - def int_AMDIL_acos : GCCBuiltin<"__amdil_acos">,
> - UnaryIntFloat;
> - def int_AMDIL_atan : GCCBuiltin<"__amdil_atan">,
> - UnaryIntFloat;
> - def int_AMDIL_asin : GCCBuiltin<"__amdil_asin">,
> - UnaryIntFloat;
> - def int_AMDIL_cos : GCCBuiltin<"__amdil_cos">,
> - UnaryIntFloat;
> - def int_AMDIL_cos_vec : GCCBuiltin<"__amdil_cos_vec">,
> - UnaryIntFloat;
> - def int_AMDIL_tan : GCCBuiltin<"__amdil_tan">,
> - UnaryIntFloat;
> - def int_AMDIL_sin : GCCBuiltin<"__amdil_sin">,
> - UnaryIntFloat;
> - def int_AMDIL_sin_vec : GCCBuiltin<"__amdil_sin_vec">,
> - UnaryIntFloat;
> - def int_AMDIL_pow : GCCBuiltin<"__amdil_pow">, BinaryIntFloat;
> - def int_AMDIL_div : GCCBuiltin<"__amdil_div">, BinaryIntFloat;
> - def int_AMDIL_udiv : GCCBuiltin<"__amdil_udiv">, BinaryIntInt;
> - def int_AMDIL_sqrt: GCCBuiltin<"__amdil_sqrt">,
> - UnaryIntFloat;
> - def int_AMDIL_sqrt_vec: GCCBuiltin<"__amdil_sqrt_vec">,
> - UnaryIntFloat;
> - def int_AMDIL_exp : GCCBuiltin<"__amdil_exp">,
> - UnaryIntFloat;
> - def int_AMDIL_exp_vec : GCCBuiltin<"__amdil_exp_vec">,
> - UnaryIntFloat;
> - def int_AMDIL_exn : GCCBuiltin<"__amdil_exn">,
> - UnaryIntFloat;
> - def int_AMDIL_log_vec : GCCBuiltin<"__amdil_log_vec">,
> - UnaryIntFloat;
> - def int_AMDIL_ln : GCCBuiltin<"__amdil_ln">,
> - UnaryIntFloat;
> - def int_AMDIL_sign: GCCBuiltin<"__amdil_sign">,
> - UnaryIntFloat;
> - def int_AMDIL_fma: GCCBuiltin<"__amdil_fma">,
> - TernaryIntFloat;
> - def int_AMDIL_rsq : GCCBuiltin<"__amdil_rsq">,
> - UnaryIntFloat;
> - def int_AMDIL_rsq_vec : GCCBuiltin<"__amdil_rsq_vec">,
> - UnaryIntFloat;
> - def int_AMDIL_length : GCCBuiltin<"__amdil_length">,
> - UnaryIntFloat;
> - def int_AMDIL_lerp : GCCBuiltin<"__amdil_lerp">,
> - TernaryIntFloat;
> - def int_AMDIL_media_sad4 : GCCBuiltin<"__amdil_sad4">,
> - Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty,
> - llvm_v4i32_ty, llvm_i32_ty], []>;
> -
> - def int_AMDIL_frexp_f64 : GCCBuiltin<"__amdil_frexp">,
> - Intrinsic<[llvm_v2i64_ty], [llvm_double_ty], []>;
> - def int_AMDIL_ldexp : GCCBuiltin<"__amdil_ldexp">,
> - Intrinsic<[llvm_anyfloat_ty], [llvm_anyfloat_ty, llvm_anyint_ty], []>;
> - def int_AMDIL_drcp : GCCBuiltin<"__amdil_rcp">,
> - Intrinsic<[llvm_double_ty], [llvm_double_ty], []>;
> - def int_AMDIL_convert_f16_f32 : GCCBuiltin<"__amdil_half_to_float">,
> - ConvertIntITOF;
> - def int_AMDIL_convert_f32_f16 : GCCBuiltin<"__amdil_float_to_half">,
> - ConvertIntFTOI;
> - def int_AMDIL_convert_f32_i32_rpi : GCCBuiltin<"__amdil_float_to_int_rpi">,
> - ConvertIntFTOI;
> - def int_AMDIL_convert_f32_i32_flr : GCCBuiltin<"__amdil_float_to_int_flr">,
> - ConvertIntFTOI;
> - def int_AMDIL_convert_f32_f16_near : GCCBuiltin<"__amdil_float_to_half_near">,
> - ConvertIntFTOI;
> - def int_AMDIL_convert_f32_f16_neg_inf : GCCBuiltin<"__amdil_float_to_half_neg_inf">,
> - ConvertIntFTOI;
> - def int_AMDIL_convert_f32_f16_plus_inf : GCCBuiltin<"__amdil_float_to_half_plus_inf">,
> - ConvertIntFTOI;
> - def int_AMDIL_media_convert_f2v4u8 : GCCBuiltin<"__amdil_f_2_u4">,
> - Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], []>;
> - def int_AMDIL_media_unpack_byte_0 : GCCBuiltin<"__amdil_unpack_0">,
> - ConvertIntITOF;
> - def int_AMDIL_media_unpack_byte_1 : GCCBuiltin<"__amdil_unpack_1">,
> - ConvertIntITOF;
> - def int_AMDIL_media_unpack_byte_2 : GCCBuiltin<"__amdil_unpack_2">,
> - ConvertIntITOF;
> - def int_AMDIL_media_unpack_byte_3 : GCCBuiltin<"__amdil_unpack_3">,
> - ConvertIntITOF;
> - def int_AMDIL_dp2_add : GCCBuiltin<"__amdil_dp2_add">,
> - Intrinsic<[llvm_float_ty], [llvm_v2f32_ty,
> - llvm_v2f32_ty, llvm_float_ty], []>;
> - def int_AMDIL_dp2 : GCCBuiltin<"__amdil_dp2">,
> - Intrinsic<[llvm_float_ty], [llvm_v2f32_ty,
> - llvm_v2f32_ty], []>;
> - def int_AMDIL_dp3 : GCCBuiltin<"__amdil_dp3">,
> - Intrinsic<[llvm_float_ty], [llvm_v4f32_ty,
> - llvm_v4f32_ty], []>;
> - def int_AMDIL_dp4 : GCCBuiltin<"__amdil_dp4">,
> - Intrinsic<[llvm_float_ty], [llvm_v4f32_ty,
> - llvm_v4f32_ty], []>;
> -}
> Index: lib/Target/R600/SIInstructions.td
> ===================================================================
> --- lib/Target/R600/SIInstructions.td
> +++ lib/Target/R600/SIInstructions.td
> @@ -2004,7 +2004,7 @@
> }
>
> def : Pat <
> - (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
> + (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
> (FCLAMP_SI f32:$src)
> >;
>
> Index: test/CodeGen/R600/llvm.rint.ll
> ===================================================================
> --- test/CodeGen/R600/llvm.rint.ll
> +++ test/CodeGen/R600/llvm.rint.ll
> @@ -1,31 +1,31 @@
> ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
> ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
>
> -; FUNC-LABEL: @f32
> +; FUNC-LABEL: @rint_f32
> ; R600: RNDNE
>
> ; SI: V_RNDNE_F32_e32
> -define void @f32(float addrspace(1)* %out, float %in) {
> +define void @rint_f32(float addrspace(1)* %out, float %in) {
> entry:
> - %0 = call float @llvm.rint.f32(float %in)
> + %0 = call float @llvm.rint.f32(float %in) #0
> store float %0, float addrspace(1)* %out
> ret void
> }
>
> -; FUNC-LABEL: @v2f32
> +; FUNC-LABEL: @rint_v2f32
> ; R600: RNDNE
> ; R600: RNDNE
>
> ; SI: V_RNDNE_F32_e32
> ; SI: V_RNDNE_F32_e32
> -define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
> +define void @rint_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
> entry:
> - %0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in)
> + %0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in) #0
> store <2 x float> %0, <2 x float> addrspace(1)* %out
> ret void
> }
>
> -; FUNC-LABEL: @v4f32
> +; FUNC-LABEL: @rint_v4f32
> ; R600: RNDNE
> ; R600: RNDNE
> ; R600: RNDNE
> @@ -35,15 +35,27 @@
> ; SI: V_RNDNE_F32_e32
> ; SI: V_RNDNE_F32_e32
> ; SI: V_RNDNE_F32_e32
> -define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
> +define void @rint_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
> entry:
> - %0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in)
> + %0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in) #0
> store <4 x float> %0, <4 x float> addrspace(1)* %out
> ret void
> }
>
> +; FUNC-LABEL: @legacy_amdil_round_nearest_f32
> +; R600: RNDNE
> +
> +; SI: V_RNDNE_F32_e32
> +define void @legacy_amdil_round_nearest_f32(float addrspace(1)* %out, float %in) {
> +entry:
> + %0 = call float @llvm.AMDIL.round.nearest.f32(float %in) #0
> + store float %0, float addrspace(1)* %out
> + ret void
> +}
> +
> +declare float @llvm.AMDIL.round.nearest.f32(float) #0
> declare float @llvm.rint.f32(float) #0
> declare <2 x float> @llvm.rint.v2f32(<2 x float>) #0
> declare <4 x float> @llvm.rint.v4f32(<4 x float>) #0
>
> -attributes #0 = { nounwind readonly }
> +attributes #0 = { nounwind readnone }
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