[PATCH] R600/SI: Add a VALU pattern for i64 xor

[Tom Stellard]

On Thu, Jun 12, 2014 at 01:00:54PM -0700, Matt Arsenault wrote:
> On 06/12/2014 12:04 PM, Tom Stellard wrote:
> > ---
> >   lib/Target/R600/SIInstructions.td | 11 +++++++----
> >   test/CodeGen/R600/xor.ll          | 27 +++++++++++++++++++++++++++
> >   2 files changed, 34 insertions(+), 4 deletions(-)
> >
> > diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> > index acdbc9b..7caf414 100644
> > --- a/lib/Target/R600/SIInstructions.td
> > +++ b/lib/Target/R600/SIInstructions.td
> > @@ -1735,15 +1735,18 @@ def : Pat <
> >   // VOP2 Patterns
> >   //===----------------------------------------------------------------------===//
> >   
> > -def : Pat <
> > -  (or i64:$src0, i64:$src1),
> > +class BinOp64Pat <SDNode node, Instruction inst> : Pat <
> > +  (node i64:$src0, i64:$src1),
> >     (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
> > -    (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
> > +    (inst  (EXTRACT_SUBREG i64:$src0, sub0),
> >                     (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
> > -    (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
> > +    (inst (EXTRACT_SUBREG i64:$src0, sub1),
> >                     (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
> >   >;
> >   
> > +def : BinOp64Pat <or, V_OR_B32_e32>;
> > +def : BinOp64Pat <xor, V_XOR_B32_e32>;
> > +
> >   class SextInReg <ValueType vt, int ShiftAmt> : Pat <
> >     (sext_inreg i32:$src0, vt),
> >     (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
> > diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll
> > index 0043041..c60aba7 100644
> > --- a/test/CodeGen/R600/xor.ll
> > +++ b/test/CodeGen/R600/xor.ll
> > @@ -91,6 +91,7 @@ define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32
> >     ret void
> >   }
> >   
> > +<<<<<<< HEAD
> Conflict marker
> 

Here is an update patch.

-Tom

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