[PATCH] ARMEB: Vector extend operations

[James Molloy]

Hi Christian,

Could you please explain why this is necessary? I'm somewhat confused.

We have canonicalised on using LD1 for vector loads, and our register content is in the form "as if" loaded by an LD1. I therefore do not understand why you need a VREV32 after the LD1. The lane order should be correct, and all you need to do is lengthen.

In fact, we chose LD1 as our form **precisely because** we didn't want to change the vectorizer!

Cheers,

James

http://reviews.llvm.org/D4043