Ran out of registers error in llc
Danna bib
danna1364 at gmail.com
Wed Jun 11 18:31:51 PDT 2014
Hi Dear Quentin,
Thank you for your response.
I ran bugpoint, and attach the outputs to this email. Hopefully they help.
My command line is this:
~/Desktop/Mibench/consumer/jpeg/jpeg-6a$ llc -reserveRegs=true
-march=arm -O0 cjpeg.ll -o cjpeg.s
error: ran out of registers during register allocation
For running bugponit I used this:
bugpoint cjpeg.ll -llc-safe --safe-tool-args -reserveRegs=true
-march=arm -O0 | tee bugpoint.txt
My goal is duplication of almost all assembly instructions (for applying
some fault-tolerant method), So, I need to reserve half of registers for
those duplicated instructions.
regards,
Danna
On Mon, Jun 9, 2014 at 2:43 PM, Quentin Colombet <qcolombet at apple.com>
wrote:
> Hi Danna,
>
> On Jun 2, 2014, at 10:54 AM, Danna bib <danna1364 at gmail.com> wrote:
>
> > Hello all,
> >
> > I am working with LLVM 3.4. I reserved half of arm registers in order to
> do some optimization in backend (after register allocation). It works fine
> with several SPEC2006 benchmarks, but in some of them such as gcc and
> gobmk, I got the following error.
> > "LLVM ERROR: ran out of registers during register allocation"
> > So, my question is how I can solve that problem?
>
> Without the input IR, this is hard to tell.
> Could you try to reduce a test case with bugpoint and we can try to help
> from here.
>
> The question though is why do you need to reserved so many registers?
>
> Thanks,
> -Quentin
>
> >
> > I would appreciate any advise you may have.
> >
> > regards,
> > Danna
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
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Read input file : 'cjpeg.ll'
*** All input ok
Initializing execution environment: Found llc: /home/moslem/LLVM2/build/Release+Asserts/bin/llc
Running the code generator to test for a crash: <llc>
Error running tool:
/home/moslem/LLVM2/build/Release+Asserts/bin/llc -o bugpoint-test-program-08df766.bc-5db99c3.llc.s bugpoint-test-program-08df766.bc
# In Register Scavenger
# Machine code for function jpeg_CreateCompress: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP-12]
fi#1: size=4, align=4, at location [SP-16]
fi#2: size=4, align=4, at location [SP-20]
fi#3: size=4, align=4, at location [SP-24]
fi#4: size=4, align=4, at location [SP-28]
fi#5: size=4, align=4, at location [SP-4]
fi#6: size=4, align=4, at location [SP-8]
Function Live Ins: %R0 in %vreg0, %R1 in %vreg1, %R2 in %vreg2
BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %R2 %R11 %LR
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R8<def> = MOVr %R2, pred:14, pred:%noreg, opt:%noreg
%R9<def> = MOVr %R3, pred:14, pred:%noreg, opt:%noreg
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R5<def> = SUBrr %R5, %R5, pred:14, pred:%noreg, opt:%noreg
%R5<def> = EORri %R5, 1, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 1, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%SP<def,tied1> = STMDB_UPD %SP<tied0>, pred:14, pred:%noreg, %R11<kill>, %LR<kill>; flags: FrameSetup
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R11<def> = MOVr %SP<kill>, pred:14, pred:%noreg, opt:%noreg; flags: FrameSetup
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%SP<def> = SUBri %SP<kill>, 24, pred:14, pred:%noreg, opt:%noreg; flags: FrameSetup
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R0<kill>, %R11, -4, pred:14, pred:%noreg; mem:ST4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R11, -8, pred:14, pred:%noreg; mem:ST4[%version.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R2<kill>, %SP, 12, pred:14, pred:%noreg; mem:ST4[%structsize.addr]
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 4, pred:14, pred:%noreg; mem:ST4[%mem]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -8, pred:14, pred:%noreg; mem:LD4[%version.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
CMPri %R0<kill>, 61, pred:14, pred:%noreg, %CPSR<imp-def>
Bcc <BB#2>, pred:0, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 1, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 2, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#1(16)
BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 2, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err2]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 10, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 10, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 20, pred:14, pred:%noreg; mem:ST4[%msg_code]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err13]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 61, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 61, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 24, pred:14, pred:%noreg; mem:ST4[%arrayidx4]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err35]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R1<def> = LDRi12 %R11, -8, pred:14, pred:%noreg; mem:LD4[%version.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 28, pred:14, pred:%noreg; mem:ST4[%arrayidx6]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R1<def> = LDRi12 %R0, 0, pred:14, pred:%noreg; mem:LD4[%err76]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R1<def> = LDRi12 %R1<kill>, 0, pred:14, pred:%noreg; mem:LD4[%error_exit7]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %SP<imp-def>
MSR 14, %R12, pred:14
BLX %R1<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %SP<imp-def>
%R5<def> = MOVi 2, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 2, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 3, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#2
BB#2: derived from LLVM BB %if.end
Predecessors according to CFG: BB#1
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R0<def> = LDRi12 %SP, 12, pred:14, pred:%noreg; mem:LD4[%structsize.addr]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
CMPri %R0<kill>, 360, pred:14, pred:%noreg, %CPSR<imp-def>
Bcc <BB#4>, pred:0, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 3, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 4, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#3(16)
BB#3: derived from LLVM BB %if.then9
Predecessors according to CFG: BB#2
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err108]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 19, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 19, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 20, pred:14, pred:%noreg; mem:ST4[%msg_code11]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err129]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 360, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 360, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 24, pred:14, pred:%noreg; mem:ST4[%arrayidx1510]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err1611]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = LDRi12 %SP, 12, pred:14, pred:%noreg; mem:LD4[%structsize.addr]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 28, pred:14, pred:%noreg; mem:ST4[%arrayidx19]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R1<def> = LDRi12 %R0, 0, pred:14, pred:%noreg; mem:LD4[%err2012]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R1<def> = LDRi12 %R1<kill>, 0, pred:14, pred:%noreg; mem:LD4[%error_exit2113]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %SP<imp-def>
MSR 14, %R12, pred:14
BLX %R1<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %SP<imp-def>
%R5<def> = MOVi 4, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 4, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 5, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#4
BB#4: derived from LLVM BB %if.end22
Predecessors according to CFG: BB#3
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 5, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R0<kill>, 0, pred:14, pred:%noreg; mem:LD4[%err2414]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R0<kill>, %SP, 4, pred:14, pred:%noreg; mem:ST4[%err23]
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 360, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 360, pred:14, pred:%noreg, opt:%noreg
%R2<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R8<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
MSR 14, %R12, pred:14
BL <es:__aeabi_memset>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %R1<imp-use>, %R2<imp-use>, %SP<imp-def>
%R5<def> = MOVi 5, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = LDRi12 %SP, 4, pred:14, pred:%noreg; mem:LD4[%err23]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 0, pred:14, pred:%noreg; mem:ST4[%err2515]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 12, pred:14, pred:%noreg; mem:ST4[%is_decompressor]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
MSR 14, %R12, pred:14
BL_pred <ga:@jinit_memory_mgr>, pred:14, pred:%noreg, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %SP<imp-def>
%R5<def> = MOVi 5, pred:14, pred:%noreg, opt:%noreg
%R2<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R8<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R2, %R0<kill>, 8, pred:14, pred:%noreg; mem:ST4[%progress]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R2, %R0<kill>, 20, pred:14, pred:%noreg; mem:ST4[%dest]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R2, %R0<kill>, 60, pred:14, pred:%noreg; mem:ST4[%comp_info]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R2, %SP, 8, pred:14, pred:%noreg; mem:ST4[%i]
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 5, pred:14, pred:%noreg, opt:%noreg
Successors according to CFG: BB#12
BB#12: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#4
%R6<def> = EORri %R6, 6, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#5
BB#5: derived from LLVM BB %for.cond
Live Ins: %R2
Predecessors according to CFG: BB#6 BB#12
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R0<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
CMPri %R0<kill>, 3, pred:14, pred:%noreg, %CPSR<imp-def>
Bcc <BB#7>, pred:12, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 7, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#6(124)
BB#6: derived from LLVM BB %for.inc
Live Ins: %R2
Predecessors according to CFG: BB#5
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R1<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R0<def> = ADDrsi %R1<kill>, %R0<kill>, 18, pred:14, pred:%noreg, opt:%noreg
%R4<def> = ADDrsi %R7<kill>, %R4<kill>, 18, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R2, %R0<kill>, 64, pred:14, pred:%noreg; mem:ST4[%arrayidx27]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R0<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R0<def> = ADDri %R0<kill>, 1, pred:14, pred:%noreg, opt:%noreg
%R4<def> = ADDri %R4<kill>, 1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R0<kill>, %SP, 8, pred:14, pred:%noreg; mem:ST4[%i]
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 7, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 6, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#5
BB#7: derived from LLVM BB %for.end
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 8, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R0, %SP, 8, pred:14, pred:%noreg; mem:ST4[%i]
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 8, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 9, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#8
BB#8: derived from LLVM BB %for.cond28
Live Ins: %R0
Predecessors according to CFG: BB#7 BB#9
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R1<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
CMPri %R1<kill>, 3, pred:14, pred:%noreg, %CPSR<imp-def>
Bcc <BB#10>, pred:12, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 9, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 10, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
Successors according to CFG: BB#9(124)
BB#9: derived from LLVM BB %for.inc33
Live Ins: %R0
Predecessors according to CFG: BB#8
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R1<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R2<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R8<def> = MOVr %R2, pred:14, pred:%noreg, opt:%noreg
%R1<def> = ADDrsi %R2<kill>, %R1<kill>, 18, pred:14, pred:%noreg, opt:%noreg
%R7<def> = ADDrsi %R8<kill>, %R7<kill>, 18, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R0, %R1<kill>, 80, pred:14, pred:%noreg; mem:ST4[%arrayidx31]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R1<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R2<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R8<def> = MOVr %R2, pred:14, pred:%noreg, opt:%noreg
%R1<def> = ADDrsi %R2<kill>, %R1<kill>, 18, pred:14, pred:%noreg, opt:%noreg
%R7<def> = ADDrsi %R8<kill>, %R7<kill>, 18, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R0, %R1<kill>, 96, pred:14, pred:%noreg; mem:ST4[%arrayidx32]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R1<def> = LDRi12 %SP, 8, pred:14, pred:%noreg; mem:LD4[%i]
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R1<def> = ADDri %R1<kill>, 1, pred:14, pred:%noreg, opt:%noreg
%R7<def> = ADDri %R7<kill>, 1, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %SP, 8, pred:14, pred:%noreg; mem:ST4[%i]
%R12<def> = MRS pred:14, pred:14
%R6<def> = SUBrr %R6, %R6, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 10, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 9, pred:14, pred:%noreg, opt:%noreg
MSR 14, %R12, pred:14
B <BB#8>
Successors according to CFG: BB#8
BB#10: derived from LLVM BB %for.end35
%R5<def> = EORrr %R5, %R6, pred:14, pred:%noreg, opt:%noreg
%R5<def> = CMPri 11, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<earlyclobber,def,tied2> = STR_PRE_IMM %R1<kill>, %R0<kill,tied0>, 40, pred:14, pred:%noreg; mem:ST4[%input_gamma](align=8)
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi16 0, pred:14, pred:%noreg
%R1<def,tied1> = MOVTi16 %R1<tied0>, 16368, pred:14, pred:%noreg
%R7<def> = MOVi16 0, pred:14, pred:%noreg
%R7<def,tied1> = MOVTi16 %R7<tied0>, 16368, pred:14, pred:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 4, pred:14, pred:%noreg; mem:ST4[%input_gamma+4]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%R0<def> = LDRi12 %R11, -4, pred:14, pred:%noreg; mem:LD4[%cinfo.addr]
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%R1<def> = MOVi 100, pred:14, pred:%noreg, opt:%noreg
%R7<def> = MOVi 100, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
STRi12 %R1<kill>, %R0<kill>, 16, pred:14, pred:%noreg; mem:ST4[%global_state]
%R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
%SP<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
%R12<def> = MRS pred:14, pred:14
%R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
%PC<def> = CMPrr %PC, pred:14, pred:%CPSR<imp-def>
Bcc <BB#11>, pred:1, pred:%CPSR
MSR 14, %R12, pred:14
%SP<def,tied1> = LDMIA_RET %SP<tied0>, pred:14, pred:%noreg, %R11<def>, %PC<def>
%PC<def> = MOVr %PC, pred:14, pred:%noreg, opt:%noreg
%R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
Successors according to CFG: BB#11
BB#11:
Predecessors according to CFG: BB#10
%R6<def> = EORri %R6, 3333, pred:14, pred:%noreg, opt:%noreg
%R6<def> = EORri %R6, 3333, pred:14, pred:%noreg, opt:%noreg
# End machine code for function jpeg_CreateCompress.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R9<def> = MOVr %R3, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R3
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R5<def> = CMPri 1, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R5<def> = CMPri 1, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R5<def> = CMPri 1, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R2<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#0 entry (0x3dfa650)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R5<def> = CMPri 2, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R5<def> = CMPri 2, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R5<def> = CMPri 2, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
- operand 0: %R7<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: %R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R1
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#1 if.then (0x3dfa700)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#2 if.end (0x3dfa7b0)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R5<def> = CMPri 4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R5<def> = CMPri 4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R5<def> = CMPri 4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
- operand 0: %R7<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R7<def> = CMPrr %R1, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: %R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R1
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#3 if.then9 (0x3dfa860)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R5<def> = CMPri 5, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R5<def> = CMPri 5, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R5<def> = CMPri 5, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R2<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R2<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R2<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R2<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#4 if.end22 (0x3dfa910)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#12 for.cond (0x3e55000)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#5 for.cond (0x3dfa9c0)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor! ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R5<def> = CMPri 7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R5<def> = CMPri 7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R5<def> = CMPri 7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R2<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R2<def> = CMPrr %R8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#6 for.inc (0x3dfaa70)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: %R5<def> = CMPri 8, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: %R5<def> = CMPri 8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: %R5<def> = CMPri 8, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#7 for.end (0x3dfab20)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#8 for.cond28 (0x3dfabd0)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R5<def> = CMPri 10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R5<def> = CMPri 10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R5<def> = CMPri 10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R1
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R1
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#9 for.inc33 (0x3dfac80)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R5<def> = CMPri 11, pred:14, pred:%CPSR<imp-def>
- operand 0: %R5<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R5<def> = CMPri 11, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R5<def> = CMPri 11, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R7<def> = MOVr %R1, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R1
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 0: %R1<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R1<def> = CMPrr %R7, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 0: %R0<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R0<def> = CMPrr %R4, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Using an undefined physical register ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R4<def> = MOVr %R0, pred:14, pred:%noreg, opt:%noreg
- operand 1: %R0
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 0: %R11<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R11<def> = CMPrr %R10, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %PC<def> = CMPrr %PC, pred:14, pred:%CPSR<imp-def>
- operand 0: %PC<def>
*** Bad machine code: Explicit operand marked as def ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %PC<def> = CMPrr %PC, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Explicit operand marked as implicit ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %PC<def> = CMPrr %PC, pred:14, pred:%CPSR<imp-def>
- operand 3: %CPSR<imp-def>
*** Bad machine code: Too few operands ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: MSR 14, %R12, pred:14
4 operands expected, but 3 given.
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %PC<def> = MOVr %PC, pred:14, pred:%noreg, opt:%noreg
First terminator was: %SP<def,tied1> = LDMIA_RET %SP<tied0>, pred:14, pred:%noreg, %R11<def>, %PC<def>
*** Bad machine code: Non-terminator instruction after the first terminator ***
- function: jpeg_CreateCompress
- basic block: BB#10 for.end35 (0x3dfad30)
- instruction: %R10<def> = MOVr %R11, pred:14, pred:%noreg, opt:%noreg
First terminator was: %SP<def,tied1> = LDMIA_RET %SP<tied0>, pred:14, pred:%noreg, %R11<def>, %PC<def>
LLVM ERROR: Found 386 machine code errors.
Checking to see if we can delete global inits: <llc>
*** Able to remove all global initializers!
*** Attempting to reduce the number of functions in the testcase
Checking for crash with only these functions: jpeg_CreateCompress jpeg_destroy_compress jpeg_abort_compress jpeg_suppress_tables jpeg_finish_compress jpeg_write_marker jpeg_write_tables jpeg_start_compress jpeg_write_scanlines jpeg_write_raw_data... <391 total>: <llc>Checking for crash with only these functions: expand_right_edge jpeg_make_c_derived_tbl jpeg_gen_optimal_table jinit_huff_encoder start_pass_huff encode_mcu_gather finish_pass_gather encode_mcu_huff finish_pass_huff htest_one_block... <196 total>: <llc>Checking for crash with only these functions: compute_color find_nearby_colors find_best_colors find_biggest_color_pop find_biggest_volume jinit_merged_upsampler start_pass_merged_upsample merged_2v_upsample h2v2_merged_upsample merged_1v_upsample... <98 total>: <llc>Checking for crash with only these functions: jinit_compress_master jinit_c_master_control skip_input_data term_source jpeg_calc_output_dimensions jpeg_new_colormap init_destination empty_output_buffer emit_sos jinit_c_main_controller... <49 total>: <llc>Checking for crash with only these functions: pre_process_data output_pass_setup jpeg_read_coefficients transdecode_master_selection jpeg_stdio_src jpeg_start_decompress term_source jpeg_calc_output_dimensions jpeg_new_colormap pass_startup... <25 total>: <llc>Checking for crash with only these functions: finish_pass_master write_frame_header write_scan_header jpeg_read_coefficients transdecode_master_selection jpeg_stdio_src write_file_trailer write_tables_only init_destination jinit_compress_master... <13 total>: <llc>Checking for crash with only these functions: write_tables_only finish_pass_master init_destination emit_marker jpeg_read_coefficients transdecode_master_selection jpeg_stdio_src: <llc>Checking for crash with only these functions: jpeg_stdio_src init_destination emit_marker write_tables_only: <llc>Checking for crash with only these functions: write_tables_only emit_marker: <llc>Checking for crash with only these functions: emit_marker: <llc>Checking for crash with only these functions: write_tables_only: <llc>Emitted bitcode to 'bugpoint-reduced-function.bc'
Checking for crash with only these blocks: entry for.cond for.body if.then if.end for.inc for.end if.then2 for.cond3 for.body5... <17 total>: <llc>Checking for crash with only these blocks: if.then8 for.inc14 for.body5 if.then2 for.cond if.then12 for.inc: <llc>Checking for crash with only these blocks: for.body if.end9 if.end17 entry if.then for.end for.cond3: <llc>Checking for crash with only these blocks: entry if.then for.end for.cond3 if.then8 for.inc14 for.body5 if.then2 for.cond if.then12... <11 total>: <llc>Checking for crash with only these blocks: for.body if.end9 if.end17: <llc>Checking for crash with only these blocks: if.end9 if.end17 entry if.then for.end for.cond3 if.then8 for.inc14 for.body5 if.then2... <13 total>: <llc>Checking for crash with only these blocks: if.then2 for.inc14 if.end17 for.body5 if.then12: <llc>Checking for crash with only these blocks: if.then8 entry if.end9 for.cond3: <llc>Checking for crash with only these blocks: if.end9 for.cond3 if.then2 for.inc14 if.end17 for.body5 if.then12: <llc>Checking for crash with only these blocks: if.then8 entry: <llc>Checking for crash with only these blocks: entry if.end9 for.cond3 if.then2 for.inc14 if.end17 for.body5 if.then12: <llc>Checking for crash with only these blocks: for.inc14 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2 if.end17 if.then12: <llc>Checking for crash with only these blocks: if.end17 if.then12 for.inc14 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2: <llc>Checking for crash with only these blocks: if.then2 if.end17 if.then12 for.inc14 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry: <llc>Checking for crash with only these blocks: entry if.end17 if.then12 for.inc14 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2 if.then12 for.inc14 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2 for.inc14 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2 for.body5 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2 for.inc14 for.cond3 if.end9: <llc>Checking for crash with only these blocks: entry if.then2 for.inc14 for.body5 if.end9: <llc>Emitted bitcode to 'bugpoint-reduced-blocks.bc'
Checking for crash with only 36 instructions: <llc>Checking for crash with only 18 instructions: <llc>Checking for crash with only 18 instructions: <llc>Checking for crash with only 27 instructions: <llc>Checking for crash with only 9 instructions: <llc>Checking for crash with only 32 instructions: <llc>Checking for crash with only 16 instructions: <llc>Checking for crash with only 16 instructions: <llc>Checking for crash with only 24 instructions: <llc>Checking for crash with only 12 instructions: <llc>Checking for crash with only 12 instructions: <llc>Checking for crash with only 18 instructions: <llc>Checking for crash with only 6 instructions: <llc>Checking for crash with only 21 instructions: <llc>Checking for crash with only 3 instructions: <llc>Checking for crash with only 23 instructions: <llc>Checking for crash with only 1 instruction: <llc>Checking for crash with only 23 instructions: <llc>Checking for crash with only 22 instructions: <llc>Checking for crash with only 21 instructions: <llc>Checking for crash with only 20 instructions: <llc>Checking for crash with only 19 instructions: <llc>Checking for crash with only 18 instructions: <llc>Checking for crash with only 18 instructions: <llc>Checking for crash with only 17 instructions: <llc>Checking for crash with only 16 instructions: <llc>Checking for crash with only 15 instructions: <llc>Checking for crash with only 14 instructions: <llc>Checking for crash with only 13 instructions: <llc>Checking for crash with only 12 instructions: <llc>Checking for crash with only 11 instructions: <llc>Checking for crash with only 10 instructions: <llc>Checking for crash with only 10 instructions: <llc>Checking for crash with only 9 instructions: <llc>Checking for crash with only 8 instructions: <llc>Checking for crash with only 7 instructions: <llc>Checking for crash with only 6 instructions: <llc>Checking for crash with only 5 instructions: <llc>Checking for crash with only 4 instructions: <llc>
*** Attempting to reduce testcase by deleting instructions: Simplification Level #1
Checking instruction: %cmp4 = icmp slt i32 undef, 4<llc>Checking instruction: %cmp7 = icmp ne %struct.JHUFF_TBL.16.1536.3056.5488.5792* undef, null<llc>Checking instruction: %cmp11 = icmp ne %struct.JHUFF_TBL.16.1536.3056.5488.5792* undef, null<llc>Checking instruction: call void @emit_marker(%struct.jpeg_compress_struct.132.84.1604.3124.5556.5860* undef, i32 217)<llc>
*** Attempting to reduce testcase by deleting instructions: Simplification Level #0
Checking instruction: %cmp4 = icmp slt i32 undef, 4<llc>Checking instruction: %cmp7 = icmp ne %struct.JHUFF_TBL.16.1536.3056.5488.5792* undef, null<llc>Checking instruction: %cmp11 = icmp ne %struct.JHUFF_TBL.16.1536.3056.5488.5792* undef, null<llc>Checking instruction: call void @emit_marker(%struct.jpeg_compress_struct.132.84.1604.3124.5556.5860* undef, i32 217)<llc>
*** Attempting to perform final cleanups: <llc>Emitted bitcode to 'bugpoint-reduced-simplified.bc'
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