[llvm] r210720 - [FastISel][X86] Add support for the sqrt intrinsic.

[Eric Christopher]

> +    // Unfortunatelly we can't use FastEmit_r, because the AVX version of FSQRT
> +    // is not generated by FastISel yet.
> +    // FIXME: Update this code once tablegen can handle it.

Assuming you've looked, curious about this?

-eric

> +    static const unsigned SqrtOpc[2][2] = {
> +      {X86::SQRTSSr, X86::VSQRTSSr},
> +      {X86::SQRTSDr, X86::VSQRTSDr}
> +    };
> +    bool HasAVX = Subtarget->hasAVX();
> +    unsigned Opc;
> +    const TargetRegisterClass *RC;
> +    switch (VT.SimpleTy) {
> +    default: return false;
> +    case MVT::f32: Opc = SqrtOpc[0][HasAVX]; RC = &X86::FR32RegClass; break;
> +    case MVT::f64: Opc = SqrtOpc[1][HasAVX]; RC = &X86::FR64RegClass; break;
> +    }
> +
> +    const Value *SrcVal = I.getArgOperand(0);
> +    unsigned SrcReg = getRegForValue(SrcVal);
> +
> +    if (SrcReg == 0)
> +      return false;
> +
> +    unsigned ImplicitDefReg = 0;
> +    if (HasAVX) {
> +      ImplicitDefReg = createResultReg(RC);
> +      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> +              TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
> +    }
> +
> +    unsigned ResultReg = createResultReg(RC);
> +    MachineInstrBuilder MIB;
> +    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
> +                  ResultReg);
> +
> +    if (ImplicitDefReg)
> +      MIB.addReg(ImplicitDefReg);
> +
> +    MIB.addReg(SrcReg);
> +
> +    UpdateValueMap(&I, ResultReg);
> +    return true;
> +  }
>    case Intrinsic::sadd_with_overflow:
>    case Intrinsic::uadd_with_overflow:
>    case Intrinsic::ssub_with_overflow:
>
> Added: llvm/trunk/test/CodeGen/X86/sqrt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sqrt.ll?rev=210720&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sqrt.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/sqrt.ll Wed Jun 11 18:11:02 2014
> @@ -0,0 +1,26 @@
> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2                             | FileCheck %s --check-prefix=SSE2
> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=SSE2
> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx                             | FileCheck %s --check-prefix=AVX
> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=AVX
> +
> +define float @test_sqrt_f32(float %a) {
> +; SSE2-LABEL: test_sqrt_f32
> +; SSE2:       sqrtss %xmm0, %xmm0
> +; AVX-LABEL:  test_sqrt_f32
> +; AVX:        vsqrtss %xmm0, %xmm0
> +  %res = call float @llvm.sqrt.f32(float %a)
> +  ret float %res
> +}
> +declare float @llvm.sqrt.f32(float) nounwind readnone
> +
> +define double @test_sqrt_f64(double %a) {
> +; SSE2-LABEL: test_sqrt_f64
> +; SSE2:       sqrtsd %xmm0, %xmm0
> +; AVX-LABEL:  test_sqrt_f64
> +; AVX:        vsqrtsd %xmm0, %xmm0
> +  %res = call double @llvm.sqrt.f64(double %a)
> +  ret double %res
> +}
> +declare double @llvm.sqrt.f64(double) nounwind readnone
> +
> +
>
>
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